Fully-depleted castellated gate MOSFET device and method of manufacture thereof

• US 20050056892A1
• Filed: 09/13/2004
• Published: 03/17/2005
• Est. Priority Date: 09/15/2003
• Status: Active Grant

• Current Assignee: Palo Alto Networks Incorporated
• Original Assignee: John J. Seliskar
• Inventors: Seliskar, John J.
• Granted Patent: US 7,211,864 B2
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device

Abstract

A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements. The gate structure also includes a top gate member which interconnects the gate elements at their upper vertical ends to cover the channel elements. Finally, a dielectric layer is provided to separate the conductive channel elements from the gate structure.

Claims

1. A castellated-gate MOSFET device capable of fully depleted operation comprising:

a semiconductor substrate body having an upper portion with a top surface and a lower portion with a bottom surface;

a source region, a drain region, and a channel-forming region disposed between said source and drain regions, all of which are formed in said semiconductor substrate body;

trench isolation insulator islands surrounding said source and drain regions as well as said channel-forming region and having upper and lower surfaces;

said channel-forming region comprising a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along said device between said source and drain regions;

a gate structure in the form of a plurality of spaced, castellated gate elements interposed between said channel elements, and a top gate member interconnecting said gate elements at their upper vertical ends to cover said channel elements; and

a dielectric layer separating said conductive channel elements from said gate structure.

2. The device as claimed in claim 1, wherein said device further includes a buried oxide layer formed in said semiconductor body lower portion beneath said source and drain regions.

3. The device as claimed in claim 2, wherein said buried oxide layer is spaced below the bottom surface of said trench isolation islands to form a common semiconductor connection in the lower portion of said device.

4. The device as claimed in claim 2, wherein said buried oxide layer abuts the bottom surface of said shallow trench isolation islands and said channel-forming region.

5. The device as claimed in claim 1, wherein said source and drain regions are each dually doped.

6. The device as claimed in claim 5, wherein the upper portion of each said source and drain region is doped n-type while the lower portions of said source and drain regions are doped p-type, forming an actual pn-junction is each said source and drain region.

7. The device as claimed in claim 6, wherein the dopant of said semiconductor substrate is of a first conductivity type, wherein the dopant of the upper portions of said source and drain regions is of a second conductivity type, and wherein the dopant of the lower portions of said source and drain regions is of said first conductivity type but of an order of magnitude greater than the dopant level of said substrate.

8. An improved fully-depleted castellated-gate MOSFET device having robust I/O applications, said device comprising:

a silicon semiconductor substrate having an upper portion with a top surface and a lower portion with a bottom surface;

a source region, a drain region, and a channel-forming region disposed between said source and drain regions, all of which are formed in said semiconductor substrate body;

trench isolation insulator islands having upper and lower surfaces and surrounding said source and drain regions and said channel-forming region;

said channel-forming region comprising a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along said device between said source and drain regions;

a gate structure in the form of a plurality of spaced, castellated conductive gate elements interposed longitudinally between and outside of said channel elements, and a top gate member interconnecting said gate elements at their upper vertical ends to cover said channel elements, said gate elements having a depth less than the lower surface of said shallow trench isolation islands;

a dielectric layer separating said conductive channel elements from said gate structure; and

a buried insulator layer formed in said semiconductor body lower portion beneath said source and drain regions.

9. The device as claimed in claim 8, wherein the outermost gate elements of said plurality of longitudinally spanning gate elements simultaneously penetrate into both said silicon substrate and said bounding shallow trench isolation oxide islands.

10. The device as claimed in claim 8, wherein said device further includes contact elements extending from said source and drain regions to said semiconductor substrate top surface to provide higher series resistance beneficial in enhancing ESD characteristics of said device.

11. The device as claimed in claim 8, wherein said source and drain regions of said device are preferably each a composite of n-type and p-type dopant impurities.

12. The device as claimed in claim 11, wherein said device is an NMOS-type device, and wherein said source and drain regions each include an upper portion doped n-type and a lower portion heavily doped p-type to form a pn-junction in said substrate.

13. The device as claimed in claim 12, wherein an electrical connection is provided to said channel elements such that the peak of the doping profile is roughly coincident with the depth of said gate element thereby forming a channel stop.

14. The device as claimed in claim 11, wherein said silicon substrate comprises a silicon-on-insulator substrate.

15. The device as claimed in claim 14, wherein said channels are of a first conductivity type, and said source and drain regions comprise single-layers of a second conductivity type.

16. The device as claimed in claim 8, wherein the dopant of said semiconductor substrate is of a first conductivity type, wherein the dopant of the upper portions of said source and drain regions is of a second conductivity type, wherein the dopant of the lower portions of said source and drain regions is of said first conductivity type but of an order of magnitude greater than the dopant level of said substrate, and wherein said buried implant layer is also of said first conductivity type and at a substantially higher concentration level than said substrate dopant level.

17. The device as claimed in claim 8, wherein said gate element material is selected from the group consisting of polysilicon, tungsten, titanium, tantalum and composites thereof, and wherein said dielectric layer is selected from the group consisting of silicon dioxide, lanthanum oxide, hafnium oxide, oxynitride (ONO), and silicon nitride.

18. The device as claimed in claim 17, wherein said conducting gate elements are made from n-type insitu-doped polysilicon patterned so as to simultaneously connect all formed gate elements with a common conducting strap, and wherein said dielectric layer comprises silicon dioxide.

19. The device as claimed in claim 8, wherein said substrate is selected from the group consisting of bulk, epitaxial, and bonded silicon wafers, preferably with an active layer of 110-crystaline orientation, engineered substrates containing strained silicon layers and/or silicon-germanium heterostructures, and engineered substrates including silicon carbide wafers with or without deposited active layers.

20. The device as claimed in claim 8, wherein said device further includes contact elements extending from said semiconductor substrate top surface and penetrating into said source and drain regions a depth less than that of said gate elements, thereby reducing current crowding effects and device series resistance.

21. A method of manufacturing a fully-depleted castellated-gate MOSFET device comprising the steps of:

creating a starting silicon semiconductor substrate;

applying active layer pad nitride masks to form trench isolation islands in said substrate;

forming a plurality of thin silicon channel elements by etching a plurality of spaced gate slots to a first predetermined depth into said substrate;

filling said slots with a dielectric material;

clearing out an area of said dielectric material within said gate slots to form a spacer and bottom gate;

depositing a gate dielectric;

filling said slot regions with a conductive gate material and connecting them together at their upper end surfaces with a top gate layer; and

implanting a source and a drain region at opposite end portions of said spaced, channel elements.

22. The method as claimed in claim 21, wherein said method further includes the step of laying out contact masks as to be directly in-line with said conductive channel elements to provide reduced device series resistance to enhance device performance.

23. The method as claimed in claim 21, wherein said semiconductor substrate comprises a silicon-on-insulator wafer, and wherein said spaced gate slots are etched to the same depth as said shallow trench isolation islands and all the way to said buried insulator layer.

24. The method as claimed in claim 21, wherein said silicon substrate is doped with a first conductivity type, and wherein said source and drain regions are each separated into an upper portion doped with a second conductivity type and a lower portion doped with said first conductivity type but at a substantially higher concentration level than the first conductivity type dopant concentration in said substrate.

25. The method as claimed in claim 21, wherein the step of forming said silicon channel elements includes the application of two outer-most gate-slot mask shapes spanning both sides of the active region as defined by the active layer mask in order to eliminate leakage and maintain fully-depleted operation in the two outer-most silicon channels elements.

26. The method as claimed in claim 21, wherein said first predetermined depth of said gate slots is less than the depth of said shallow trench isolation islands, and wherein said gate slot trenches are filled with an oxide dielectric, planarized and then re-etched to a second predetermined depth which is less than said first predetermined depth, simultaneously forming a thick bottom gate oxide and spacers between a gate conductor, which will fill said gate slots and said source and drain regions.

27. The method as claimed in claim 26, wherein said oxide dielectric material used to fill the gate slots, and later partially removed, is selected from a group consisting of silicon dioxide, CVD diamond, oxynitride (ONO), and silicon nitride.

28. The method as claimed in claim 26, wherein said first and second predetermined depths may both fall within a range of 250 to 1200 nanometers.

29. The method as claimed in claim 21, wherein outermost gate slot masks are provided to form the outermost gate conductor elements which simultaneously penetrate into both said silicon substrate and bounding shallow trench isolation islands.

30. The method as claimed in claim 21, wherein said device is a dual-gate device, and wherein a nitride cap may reside on top of said conducting elements thereby shutting off said top gate layer.

31. The method as claimed in claim 30, wherein bottom gate implants are provided in said device by adding an additional mask layer with associated processing thereof.

32. The method as claimed in claim 21, wherein contacts are provided to said source and drain regions coincident with the upper surface of said silicon substrate to result in higher series resistance by applying contact masks as to be directly in-line with said conductive channel elements.

33. A method of manufacturing a fully-depleted castellated-gate MOSFET device comprising the steps of:

creating a starting silicon semiconductor substrate;

applying active layer pad nitrate masks to form shallow trench isolation islands in said substrate;

removing said nitride masks using hot phosphoric acid;

forming a plurality of thin silicon channel elements by etching a plurality of spaced gate slots to a first predetermined depth into the substrate;

planarizing the upper surface of said substrate by utilizing said pad nitride layer as a CMP etch stop;

depositing a thin linear dielectric oxide to fill said patterned gate slots;

clearing out an area of said dielectric material within said gate slots to form a spacer and bottom gate;

depositing a gate dielectric;

filling said slot regions with a conductive gate material and connecting them together at their upper end surfaces with a top gate layer; and

implanting a source and a drain region at opposite end portions of said spaced, channel pillars.

34. The method as claimed in claim 33, wherein gate slot masks are provided to overlap a gate mask in the direction of channel element length, with the amount of the overlap representing the spacer and wherein said gate mask overlaps said gate slot masks by a predetermined distance in the direction of the width of said device orthogonal to the channel element length.

35. The method as claimed in claim 33, wherein said device comprises an NMOS device, wherein said silicon semiconductor substrate comprises a silicon-on-insulator starting substrate, wherein said buried oxide layer abuts the bottom of said substrate and said shallow trench isolation islands, and wherein said gate slots are etched to the same depth as said shallow trench isolation islands.

36. The method as claimed in claim 33, wherein an additional low energy implant is performed to further increase the threshold of the bottom single-gate parasitic device.

37. The method as claimed in claim 33, wherein said gate dielectric layer has a thickness in the range of 70 to 150 angstroms in order to support operating voltages in the range of 2.5 to 5.0 volts.

38. The method as claimed in claim 33, wherein after the formation of said gate dielectric, a gate stack is deposed consisting of a gate conductor, an oxide which serves as an etch stop, and a silicon nitride cap, said silicon nitride having significant ion-implant stopping power as the result of its higher material density which enables the self-aligned source and drain implants to be performed without counter-doping non-metal gate materials or the device channel itself.

39. The method as claimed in claim 33, wherein a light oxidizing anneal is performed when said gate conductor is a non-metal to passivate exposed silicon areas with a thin oxide as well as to consume any stringers that may result from said etch process.

40. The method as claimed in claim 33, wherein said source and drain regions are relatively deep and necessitates the step of applying a gate capping layer in order to prevent counter-doping of said top gate layer and the channel elements under said gate.

41. A method of manufacturing a fully-depleted castellated-gate MOSFET device comprising the steps of:

creating a starting silicon semiconductor substrate;

applying active layer pad nitride masks to form shallow trench isolation islands in said substrate;

removing said nitride masks using hot phosphoric acid;

forming a plurality of thin silicon channel elements by etching a plurality of spaced gate slots to a first predetermined depth into the substrate;

planarizing the upper surface of said substrate by utilizing said pad nitride layer as a CMP etch stop;

depositing a thin linear dielectric oxide to fill said patterned gate slots;

forming a dummy gate structure by depositing and patterning a film material;

implanting source and drain regions that are consequently self-aligned by said dummy gate structure;

forming a planarized interlevel dielectric layer by depositing an oxide and etching it back using said dummy gate structure as a CMP etch stop;

removing said dummy gate structure and underlying area of said dielectric material within said gate slots to form a spacer and bottom gate;

forming vertical gate elements by deposting a conductive gate material over said planarized interlevel dielectric layer to fill the opened areas of said slot regions; and

forming a planarized conducting strap which connects said vertical gate elements together at their upper end surfaces by using CMP to etch back upper surface of said conductive gate material to be coincident with upper surface of said interlevel dielectric layer.

42. The method as claimed in claim 41, wherein gate slot masks are provided to overlap a gate mask in the direction of channel element length, with the amount of the overlap representing the spacer, and wherein said gate mask overlaps said gate slot masks by a predetermined distance in the direction of the width of said device orthogonal to the channel element length.

43. The method as claimed in claim 41, wherein said device comprises an NMOS device, wherein said silicon semiconductor substrate comprises a silicon-on-insulator starting substrate, wherein said buried oxide layer abuts the bottom of said substrate and said shallow trench isolation islands, and wherein said gate slots are etched to the same depth as said shallow trench isolation islands.

44. The method as claimed in claim 41, wherein an additional low energy implant is performed to further increase the threshold of the bottom single-gate parasitic device.

45. The method as claimed in claim 41, wherein said gate dielectric layer has a thickness in the range of 70 to 150 angstroms to support device operating voltages in the range of 2.5 to 5.0 volts.

46. The method as claimed in claim 41, wherein after the deposition of said linear dielectric which has filled said patterned gate slots, a dummy gate stack is deposed and comprises polysilicon, an oxide which serves as an etch stop, and a silicon nitride cap, said silicon nitride having significant ion-implant stopping power as the result of its higher material density to enable the self-aligned source and drain implants to be performed without counter-doping.

47. The method as claimed in claim 41, wherein a light oxidizing anneal is performed when said dummy gate stack contains a bottom layer of polysilicon to consume any stringers that may result from said patterning process.