Digital clamp circuit

• US 20050057693A1
• Filed: 08/12/2004
• Published: 03/17/2005
• Est. Priority Date: 09/11/2003
• Status: Abandoned Application

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakakuki, Toshio
• Application Number:
  US10/916,859
• Publication Number:
  US 20050057693A1
• Time in Patent Office: Days
• US Class Current: 348/695
• CPC Class Codes: H04N 5/185 for the black level

Abstract

A digital clamp circuit is composed of a clamp circuit and a clamp level generation circuit. The clamp level generation circuit compares the average reference black level BL of a signal Y0 for each frame with a clamp level, stores the comparison result, and then updates a clamp level which is stored in accordance with the comparison results for every predetermined number of frames.

Claims

1. A digital clamp circuit for clamping a digital video signal which represents a subject image in frame units, a reference black signal and a subject signal periodically appearing for each frame of the digital video signal, the digital clamp circuit comprising:

a clamp circuit for clamping the reference black signal of the digital video signal to a predetermined level; and

a clamp level generation circuit for generating a clamp level by which clamping is performed in the clamp circuit,

wherein the clamp level generation circuit includes a comparator circuit for comparing the reference black signal for a plurality of frames with an existing clamp level.

2. A digital clamp circuit according to claim 1, wherein

the clamp level generation circuit updates the clamp level based on a comparison result of the comparator circuit.

3. A digital clamp circuit according to claim 1, wherein

the clamp level generation circuit includes:

a clamp level memory for storing the clamp level; and

an update circuit for updating the clamp level stored in the clamp level memory based on a comparison result of the comparator circuit.

4. A digital clamp circuit according to claim 3, wherein

the update circuit includes:

a comparison result register for storing the comparison result of the comparison circuit as a register value;

a determination circuit for updating the clamp level stored in the clamp memory based on the register value of the comparison result register; and

a frame counter for causing the determination circuit to operate and also outputting an update clock signal for resetting the comparison result register for every said plurality of frames.

5. A digital clamp circuit according to claim 3, wherein

the update circuit includes:

a comparison result memory for storing the comparison results of the comparator circuit corresponding to a plurality of frames; and

a determination circuit for updating the clamp level stored in the clamp level memory based on a content of the comparison result memory.