Method for operating a memory device

• US 20050058005A1
• Filed: 12/30/2003
• Published: 03/17/2005
• Est. Priority Date: 01/31/2002
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Shappir, Assaf, Avni, Dror
• Granted Patent: US 7,079,420 B2
• Time in Patent Office: Days
• US Class Current: 365/232
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Claims

1. A method of operating a set of memory cells in a memory array, the method comprising:

applying a first operating pulse to a terminal of a first cell, wherein the first operating pulse is intended to place the first cell into a predefined state; and

applying a second operating pulse to a terminal of a second cell,

wherein the second operating pulse is intended to place the second cell to the predefined state, and

wherein the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

2. The method according to claim 1, further comprising a step of applying a third operating pulse to a terminal of a third cell,

wherein the third operating pulse is intended to place the third cell to said predefined state, and

wherein the pulse characteristics of the third pulse are a function of the response of the first and the second cells to the first and the second operating pulses, respectively.

3. The method according to claim 1, wherein said pulse characteristics of the second operating pulse are adjusted by adjusting the duration of the second operation pulse.

4. The method according to claim 1, wherein said pulse characteristics of the second operation pulse are adjusted by adjusting the amplitude of said second operation pulse.

5. A control circuit for operating a set of memory cells in a memory array, said control circuit comprising:

a charge circuit adapted to produce a first operating pulse to a terminal of a first cell intended to place the first cell into a predefined state; and

a logic unit adapted to determine pulse characteristics of a second operating pulse as a function of the response of the first cell to the first operating pulse.

6. The control circuit according to claim 5, wherein said logic unit is further adapted to determine pulse characteristics of a third operating pulse as a function of the response of the first cell and the second cell to the first and second operating pulses, respectively.

7. The control circuit according to claim 5, wherein said logic unit is adapted to adjust the duration of said second operation pulse.

8. The control circuit according to claim 5, wherein said logic unit is adapted to adjust the amplitude of said second operation pulse.

9. The control circuit according to claim 5, further comprising a memory buffer adapted to store data received from the set of memory cells.

10. A system for operating a set of memory cells in a memory array, said system comprising:

a memory array;

a sense amplifier adapted to determine a response of operated cells; and

a control circuit adapted to produce a first operating pulse to a terminal of a first cell intended to place the first cell into a predefined state; and

adapted to determine pulse characteristics of a second operating pulse as a function of the response of the first cell to the first operating pulse.

11. The system according to claim 10, wherein said control circuit is further adapted to determine pulse characteristics of a third operating pulse as a function of the response of the first cell and the second cell to the first and second operating pulses, respectively.

12. The system according to claim 10, wherein said control circuit is adapted to adjust the duration of said second operation pulse.

13. The system according to claim 10, wherein said control circuit is adapted to adjust the amplitude of said second operation pulse.