Frequency domain equalizer for wireless communications system

• US 20050058193A1
• Filed: 09/12/2003
• Published: 03/17/2005
• Est. Priority Date: 09/12/2003
• Status: Active Grant

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Seven Generations Energy Ltd.
• Inventors: Saed, Aryan
• Granted Patent: US 7,362,802 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: H04L 2025/03414 Multicarrier
• CPC Class Codes: H04L 2025/03522 Frequency domain
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/2662 Symbol synchronisation

Abstract

The present invention relates to wireless communications and is particularly applicable to devices and modules for correcting errors introduced to a wireless signal after its transmission. An equalizer is provided which compensates for undesirable effects on received radio signals introduced by either signal processing or by the transmission medium. In operation, the equalizer multiples the complex received signal with a complex corrective signal that compensates for these effects. A tap corrective signal corrects for time-varying channel effects (i.e. channel distortions), a timing tracking signal corrects for carrier frequency offset errors, and a phase tracking signal corrects for sampling frequency offset errors.

Claims

1. A frequency domain equalization system to compensate for wireless communication time-constant and time-varying channel effects, residual carrier frequency offset and sampling frequency offset arising in a received complex signal comprising:

(a) an equalizer tap calculation circuit cooperating with an equalizer tap tracking circuit for correcting said time-constant and time-varying channel effects;

(b) a phase tracking circuit for correcting said residual carrier frequency offset; and

(d) a timing tracking circuit for correcting said sampling frequency offset,

wherein said received complex signal is inputted from a Fast Fourier Transform (FFT) circuit and a corrected complex signal is outputted to a soft decision demapper;

and wherein a corrective tap signal is generated in said equalizer tap calculation circuit for use in correcting said complex signal;

and wherein pilot signals are extracted for use in said phase and timing tracking circuits.

2. The frequency domain equalization system of claim 1 wherein said complex signal comprises 52 complex subcarriers.

3. The frequency domain equalization system of claim 2 wherein said corrective tap signal is generated by applying a sign least mean squares algorithm to said 52 complex subcarriers.

4. The frequency domain equalization system of claim 3 wherein said equalizer tap tracking circuit further includes a slicer and wherein said equalizer tap tracking circuit updates said corrective tap signal with a running time average of a slicer error.

5. The frequency domain equalization system of claim 1 wherein respective corrective tap signals are calculated for each subcarrier associated with said received complex signal.

6. The frequency domain equalization system of claim 1 wherein said equalizer tap calculation circuit also performs spectral smoothing.

7. The frequency domain equalization system of claim 1 wherein said timing tracking circuit tracks the phases of said pilot signals using time averaging.

8. The frequency domain equalization system of claim 2 wherein a respective phase and timing rotor is applied to said pilots and said 52 complex subcarriers for correction of said received complex signal.

9. The frequency domain equalization system of claim 1 wherein four pilot signals are calculated.

10. The frequency domain equalization system of claim 1 wherein said phase tracking circuit is nested within said timing tracking circuit.

11. In a wireless digital receiver, a method of correcting a received complex signal comprising:

(a) estimating a channel response from long sequence training symbols FFT 1 and FFT 2 contained in a received data packet preamble;

(b) processing pilot tones in each of said FFT 1 and FFT 2 long sequence training symbols to evaluate carrier frequency offset and sampling frequency offset;

(c) compensating for any of said carrier frequency or sampling frequency offset in a subsequently received data packet;

(d) tracking channel distortion during subsequent reception of data packets; and

(e) modifying said channel response to compensate for any detected distortion.

12. The method of claim 11 wherein said step of channel estimation is performed by comparing the received amplitude and phase of said long sequence training symbols FFT 1 and FFT 2 with a reference.

13. The method of claim 12 wherein said step of comparing further comprises averaging over said long sequence training symbols FFT 1 and FFT 2 and demodulating each subcarrier associated with said received complex signal.

14. The method of claim 11 wherein said step of estimating further comprises producing a corrective tap signal and applying said corrective tap signal to said received long sequence training symbols FFT I and FFT 2.

15. The method of claim 14 wherein said step of tracking comprises refining said corrective tap signal by tracking residual phase and timing error, and channel variations.

16. The method of claim 14 wherein said step of estimating further comprises spectral smoothing.

17. The method of claim 11 wherein said step of compensating further comprises applying respective phase and timing rotors to said pilots and subcarriers associated with said received complex signal to correct said respective carrier frequency and sampling frequency offsets.

18. The method of claim 17 wherein said step of processing further comprises tracking the phase across said pilot tones using time averaging.

19. The method of claim 11 wherein said step of processing further comprises sampling said received complex signal at an analogue to digital converter (ADC) with a clock associated with said digital receiver and determining a difference in clock frequency between said digital receiver clock and a clock associated with a transmitter.