Staggered AGC with digitally controlled VGA

• US 20050058228A1
• Filed: 09/12/2003
• Published: 03/17/2005
• Est. Priority Date: 09/12/2003
• Status: Active Grant

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Seven Generations Energy Ltd.
• Inventors: Birkett, Neil
• Granted Patent: US 7,433,431 B2
• Time in Patent Office: Days
• US Class Current: 375/345
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04L 2027/0016 Stabilisation of local oscillators

Abstract

The invention relates to the field of wireless communications, more particularly to a method of and device for automatic gain control (AGC) incorporating digitally controlled variable gain amplifiers (VGAs). The invention provides an AGC circuit comprising an I/Q baseband strip comprising multiple AGC stages wherein each of the AGC stages comprises: respective I and Q VGAs; a detector for detecting respective I and Q output signals received from the respective I and Q VGAs; an analogue to digital converter (ADC) for converting the detected I and Q output signals; and a digital engine for adjusting the respective I and Q VGAs for differences between the detected I and Q output signals and a reference signal. The use of staggered AGCs incorporating respective I and Q VGAs means that the total dynamic range is split between n-stages, thereby allowing for reduced gain requirements in the VGAs. Additionally, the use of digital control for setting the VGA gains means that analogue variations and I/Q gain imbalances are reduced. Additionally, the use of multiple update rates or magnitudes in the VGA control improves the dynamic settling time.

Claims

1. In a wireless receiver wherein a radio frequency signal is received, downconverted and processed into in-phase (I) and quadrature (Q) signal paths, a method of automatic gain control (AGC) comprising the steps of:

(a) at a specified stage in an I/Q baseband strip containing multiple automatic gain control (AGC) stages, each of said AGC stages having locally generated control signals associated therewith;

i. detecting respective I and Q output signals received from respective I and Q variable gain amplifiers (VGAs) associated with said specified AGC stage;

ii. digitizing said detected I and Q signals;

iii. adjusting with said associated control signal said respective I and Q VGAs for differences between said detected I and Q output signals and a reference signal; and

(b) repeating step (a) through each AGC stage.

2. The method of claim 1 wherein the step of detecting further comprises:

(a) passing said respective I and Q output signals through respective high pass filters (HPFs);

(b) rectifying said respective I and Q filtered output signals;

(c) adding said respective I and Q filtered output signals in an operational amplifier; and

(d) passing said added I and Q filtered output signal through a low pass filter (LPF).

3. The method of claim 1 wherein the step of digitizing further comprises:

(a) receiving in an analogue to digital converter (ADC) said added low pass filtered I and Q signal;

(b) comparing said received signals to a reference signal; and

(c) generating digital up/down and count/hold control signals.

4. The method of claim 3 wherein said step of comparing further comprises using a multi-level comparator and a logic circuit to generate said digital up/down and count/hold control signals.

5. The method of claim 4 wherein the step of adjusting further comprises:

(a) receiving in an up/down counter said up/down and count/hold control signals; and

(b) setting the gains of respective I and Q variable gain amplifiers (VGAs).

6. The method of claim 5 wherein the step of setting further comprises:

(a) if said I and Q filtered output signals fall outside a predefined boundary, modifying the gains of said respective I and Q VGAs until a desired I/Q output signal is achieved;

(b) else, maintaining said respective I and Q VGA settings.

7. The method of claim 6 wherein the step of modifying comprises adjusting said respective I and Q VGAs at a fast rate if said detected I/Q output signal is beyond a first predefined range or at a slow rate if said detected I/Q output signal is beyond a second predefined range.

8. The method of claim 6 wherein the step of modifying comprises adjusting said respective I and Q VGAs at a large magnitude if said detected I/Q output signal is beyond a first predefined range or at a small magnitude if said detected I/Q output signal is beyond a second predefined range.

9. In a wireless receiver wherein a radio frequency signal is received, downconverted and processed into in-phase (I) and quadrature (Q) signal paths, an automatic gain control (AGC) circuit comprising an I/Q baseband strip comprising multiple AGC stages wherein each of said AGC stages comprises:

(a) respective I and Q variable gain amplifiers (VGAs);

(b) a detector for detecting respective I and Q output signals received from said respective I and Q variable gain amplifiers (VGAs);

(c) an analogue to digital converter (ADC) for converting said detected I and Q output signals; and

(d) a digital engine for digitally adjusting said respective I and Q variable gain amplifiers (VGAs) for differences between said detected I and Q output signals and a reference signal.

10. The automatic gain control circuit of claim 9 wherein said detector comprises:

i. respective I and Q high pass filters (HPFs) for removing direct current (DC) offsets from said respective I and Q output signals;

ii. a rectifier communicating with said respective I and Q HPFs for changing said respective filtered I and Q output signals from alternating current (AC) to direct current (DC);

iii. an operational amplifier (Op-amp) communicating with said rectifier for adding said filtered I and Q output signals; and

iv. a low pass filter (LPF) communicating with said Op-amp for filtering said added I and Q output signals.

11. The automatic gain control circuit of claim 10 wherein said ADC comprises a multi-level comparator and a logic circuit.

12. The automatic gain control circuit of claim 11 wherein the number of levels in said multi-level comparator is at least four.

13. The automatic gain control circuit of claim 12 wherein said digital engine comprises an up/down counter for setting gains associated with said respective I and Q variable gain amplifiers (VGAs).

14. In a wireless receiver wherein a radio frequency signal is received, downconverted and processed into in-phase (I) and quadrature (Q) signal paths, an automatic gain control (AGC) circuit comprising an I/Q baseband strip comprising at least two AGC stages wherein each of said AGC stages comprises:

(a) respective I and Q variable gain amplifiers (VGAs); and

(b) a closed feedback loop providing respective digital control signals to said respective I and Q variable gain amplifiers.

15. The automatic gain control circuit of claim 14 wherein said closed feedback loop comprises:

i. a detector for detecting respective I and Q output signals received from said respective I and Q variable gain amplifiers (VGAs);

ii. an analogue to digital converter (ADC) for converting said detected I and Q output signals; and

iii. a digital engine for digitally adjusting said respective I and Q variable gain amplifiers (VGAs) for differences between said detected I and Q output signals and a reference signal.

16. The automatic gain control circuit of claim 15 wherein said closed feedback loop is positioned before said respective I and Q variable gain amplifiers (VGAs).

17. The automatic gain control circuit of claim 15 wherein said closed feedback loop is positioned after said respective I and Q variable gain amplifiers (VGAs).

18. In a wireless receiver wherein a radio frequency signal is received, downconverted and processed into in-phase (I) and quadrature (Q) signal paths, a method of automatic gain control (AGC) comprising, at a specified stage in an I/Q baseband strip containing at least two automatic gain control (AGC) stages, each of said AGC stages having respective I and Q variable gain amplifiers (VGAs) associated therewith, providing locally generated respective I and Q digital control signals to said respective I and Q VGAs through a closed feedback loop associated with said specified AGC stage.

19. The method of claim 19 wherein the step of providing comprises:

i. detecting respective I and Q output signals received from said respective I and Q variable gain amplifiers (VGAs);

ii. digitizing said detected I and Q signals; and

iii. adjusting with said associated control signal said respective I and Q VGAs for differences between said detected I and Q output signals and a reference signal.