Analog to digital signal conditioning in optoelectronic transceivers

• US 20050058455A1
• Filed: 04/02/2004
• Published: 03/17/2005
• Est. Priority Date: 02/05/2001
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Hosking, Lucy G., Dybsetter, Gerald L., Aronson, Lewis B., Hahin, Jayne Catherine, Case, Daniel
• Granted Patent: US 7,346,278 B2
• Time in Patent Office: Days
• US Class Current: 398/135
• CPC Class Codes: H04B 10/07 Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
• CPC Class Codes: H04B 10/0799 Monitoring line transmitter or line receiver equipment
• CPC Class Codes: H04B 10/43 using a single component as both light source and receiver, e.g. using a photoemitter as a photoreceiver
• CPC Class Codes: H04B 2210/08 Shut-down or eye-safety

Abstract

Circuitry for monitoring the operation of an optoelectronic transceiver includes a sequence of interconnected signal processing circuits for processing an analog input signal and producing a digital result signal, where the analog signal represents one or more operating conditions of the optoelectronic transceiver. The sequence of signal processing circuits include gain circuitry for amplifying or attenuating the analog input signal by a gain value to produce a scaled analog signal, an analog to digital converter for converting the scaled analog signal into a first digital signal, and digital adjustment circuitry for digitally adjusting the first digital signal to produce the digital result signal. The digital adjustment circuitry includes shifting circuitry configured to shift an input digital signal in accordance with a shift value so as to produce a digital shifted signal. The digital result signal is stored in memory in predefined locations accessible by a host.

Claims

1. Circuitry for monitoring the operation of an optoelectronic transceiver, said circuitry comprising:

a sequence of interconnected signal processing circuits for processing an analog input signal and producing a digital result signal, where said analog signal represents one or more operating conditions of the optoelectronic transceiver, said sequence of signal processing circuits including;

gain circuitry configured to amplify or attenuate said analog input signal by a gain value to produce a scaled analog signal;

an analog to digital converter configured to convert said scaled analog signal into a first digital signal;

digital adjustment circuitry for digitally adjusting said first digital signal to produce said digital result signal, said digital adjustment circuitry including shifting circuitry configured to shift an input digital signal in accordance with a shift value so as to produce a digital shifted signal; and

memory configured to store values of said digital result signal in predefined locations accessible by a host.

2. The circuitry of claim 1, wherein said shifting circuitry is configured to right shift an input digital signal in accordance with said shift value so as to produce a digital shifted signal that has been shifted to the right.

3. The circuitry of claim 1, wherein said shifting circuitry is configured to left shift an input digital signal in accordance with said shift value so as to produce a digital shifted signal that has been shifted to the left.

4. The circuitry of claim 1, further comprising an interface for allowing the host to read from host specified locations within said memory.

5. The circuitry of claim 2, wherein said gain value is stored in a memory mapped location in the optoelectronic transceiver that is accessible to the host via said interface.

6. The circuitry of claim 2, wherein said gain value and said shift value are stored in respective memory mapped locations in the optoelectronic transceiver, and wherein said interface is configured to allow the host to access said respective memory mapped locations.

7. The circuitry of claim 1, wherein said shifting circuitry is configured to receive said input digital signal, and to shift said input digital signal by a number of bits specified by said shift value to create said digital shifted signal.

8. The circuitry of claim 1, said digital adjustment circuitry further comprising offset circuitry configured to offset said first digital signal by an offset value so as to produce the input digital signal for said shifting circuitry.

9. The circuitry of claim 1, said digital adjustment circuitry further comprising offset circuitry configured to offset said first digital signal by an offset value so as to produce the input digital signal for said shifting circuitry.

10. The circuitry of claim 1, further comprising analog offset circuitry configured to offset said analog input signal or said scaled analog signal prior to receipt by said analog to digital converter.

11. The circuitry of claim 1, wherein said analog signal comprises a sequence of analog signals representing a plurality of operating conditions of the optoelectronic transceiver, said gain value comprises a sequence of gain values, each corresponding to a respective analog signal in the sequence of analog signals, and said shift value comprises a sequence of shift values, each corresponding to a respective analog signal in the sequence of analog signals.

12. The circuitry of claim 11, wherein said plurality of operating conditions includes laser bias current, laser output power and received power.

13. The circuitry of claim 1, wherein said analog signal comprises a sequence of analog signals representing a plurality of operating conditions of the optoelectronic transceiver and the digital result signal comprises a corresponding sequence of digital result signals, said circuitry including:

comparison logic configured to compare said digital result values with limit values to generate flag values, wherein the flag values are stored in predefined flag storage locations within the memory during operation of the optoelectronic transceiver;

wherein the interface is configured to enable the host to read from the predefined flag storage locations within the memory, in accordance with commands received from the host.

14. The circuitry of claim 13, wherein said plurality of operating conditions includes laser bias current, laser output power and received power.

15. The circuitry of claim 13, wherein said plurality of operating conditions includes temperature, laser bias current, and laser output power.

16. A method of monitoring an optoelectronic device, comprising:

receiving a plurality of analog signals from the optoelectronic device, the analog signals corresponding to operating conditions of the optoelectronic device, converting the received analog signals into digital result values, and storing said digital result values in predefined locations within a memory;

wherein the converting includes;

amplifying or attenuating said analog signals by respective gain values to produce scaled analog signals;

converting said scaled analog signals into first digital signals;

digitally adjusting said first digital signals to produce said digital result values, including shifting input digital signals in accordance with a shift value so as to produce digital shifted signals.

17. The method of claim 16, including

comparing the digital result values with limit values to generate flag values, and storing the flag values in predefined flag locations within the memory;

and

in accordance with instructions received from a host device, enabling the host device to read from host-specified locations within the memory, including the predefined flag locations.

18. The method of claim 16, wherein said digitally adjusting includes right shifting input digital signals in accordance with a shift value so as to produce digital shifted signals that are shifted to the right.

19. The method of claim 16, wherein said digitally adjusting includes left shifting input digital signals in accordance with a shift value so as to produce digital shifted signals that are shifted to the left.