Thin film transistor and fabrication method for same

• US 20050059227A1
• Filed: 10/29/2004
• Published: 03/17/2005
• Est. Priority Date: 05/30/2003
• Status: Active Grant

• Current Assignee: China Star Optoelectronics International (HK) Limited (TCL Technology Group Corp.)
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wu, Yung-Fu, Chen, Chen-Ming
• Granted Patent: US 6,995,050 B2
• Time in Patent Office: Days
• US Class Current: 438/586
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A thin film transistor and a method for fabricating the same. The thin film transistor comprises a substrate and a patterned semiconductive layer formed on the substrate, wherein the semiconductive layer comprises a channel region and doped regions adjacent to the channel region. A gate insulating layer is formed on the above structure. A gate electrode is located on the gate insulating layer above the channel region. Source and drain electrodes are located on the gate insulating layer adjacent to the semiconductive layer. A dielectric layer having contact holes is formed on the above structure and a patterned conductive layer is formed on predetermined parts of the dielectric layer electrically connecting the doped regions to the source and drain electrode through the contact holes.

Claims

1. A method of fabricating a thin film transistor, requiring only four photolithography steps, comprising:

providing a substrate;

forming a semiconductive layer on the substrate;

patterning the semiconductive layer to form a semiconductor island, wherein the semiconductor island comprises a channel region and predetermined source and drain regions adjacent to the channel region;

forming a gate insulating layer and a first conductive layer sequentially on the substrate and the semiconductor island;

patterning the first conductive layer to simultaneously form a gate electrode on the gate insulating layer above the channel region and source/drain electrodes on the respective gate insulating layer adjacent to the semiconductor island;

using the gate electrode as a mask to perform a self-aligned ion implantation on the predetermined source and drain regions to form source/drain regions;

forming a dielectric layer on the gate insulating layer, the gate electrode, and the source and drain electrodes;

patterning the dielectric layer to form a plurality of contact holes via the dielectric layer and the gate insulating layer exposing part of the surface of source/drain regions and electrodes; and

forming a patterned second conductive layer on predetermined parts of the dielectric layer to electrically connect the source and drain regions to the source and drain electrodes through the contact holes.

2. The method as claimed in claim 1, further comprising, before forming the semiconductive layer on the substrate, forming a buffer layer on the substrate.

3. The method as claimed in claim 1, wherein the semiconductive layer is a crystalline silicon layer.

4. The method as claimed in claim 3, wherein the method of forming crystalline silicon layer comprises:

forming an amorphous silicon layer on the substrate; and

crystallizing the amorphous silicon layer to form the crystalline silicon layer by thermal application or excimer laser annealing (ELA) through solid or liquid phase growing.

5. The method as claimed in claim 1, wherein the thickness of the gate insulating layer is 50 nm to 150 nm.

6. The method as claimed in claim 1, wherein the thickness of the dielectric layer is 300 nm to 3000 nm

7. The method as claimed in claim 1, wherein the plurality of contact holes is formed simultaneously in one photolithography step

8. A method of fabricating a thin film transistor for transflective display employed five photolithography steps, comprising:

providing a substrate with a predetermined transmissive TFT region and a predetermined reflective TFT region;

forming a semiconductive layer on the substrate;

patterning the semiconductive layer to form a semiconductor island on the predetermined transmissive TFT region and the predetermined reflective TFT region respectively, wherein the semiconductor island comprises a channel region and predetermined source and drain regions adjacent to the channel region;

forming a gate insulating layer and a first conductive layer sequentially on the substrate and the semiconductor islands;

patterning the first conductive layer to simultaneously form gate electrodes on the gate insulating layer above the channel regions and source/drain electrodes on the respective gate insulating layer adjacent to the semiconductor islands;

using the gate electrodes as masks to perform a self-aligned ion implantation on the predetermined source and drain regions to form source/drain regions;

forming a dielectric layer on the gate insulating layer, the gate electrodes, and the source and drain electrodes;

patterning the dielectric layer to form a plurality of contact holes via the dielectric layer and the gate insulating layer exposing part of the surface of source/drain regions and electrodes;

forming a patterned second conductive layer on predetermined parts of the dielectric layer for the predetermined transmissive TFT region to electrically connect the source and drain regions to the source and drain electrodes through the contact holes; and

forming a patterned third conductive layer on predetermined parts of the dielectric layer for the predetermined reflective TFT region to electrically connect the source and drain regions to the source and drain electrodes through the contact holes.

9. The method as claimed in claim 8, further comprising, before forming the semiconductive layer on the substrate, forming a buffer layer on the substrate.

10. The method as claimed in claim 8, wherein the semiconductive layer is a crystalline silicon layer.

11. The method as claimed in claim 10, wherein the method of forming the crystalline silicon layer comprises:

forming an amorphous silicon layer on the substrate; and

crystallizing the amorphous silicon layer to form the crystalline silicon layer by thermal application or excimer laser annealing (ELA) through a solid or liquid phase growing.

12. The method as claimed in claim 8, wherein the thickness of the gate insulating layer is 50 nm to 150 nm.

13. The method as claimed in claim 8, wherein the thickness of the dielectric layer is 300 nm to 3000 nm.

14. The method as claimed in claim 8, wherein the plurality of contact holes is formed simultaneously by one photolithography step.

15. A method of fabricating a CMOS thin film transistor with lightly doped drain structure, requiring only six photolithography steps, comprising:

providing a substrate with an n-type MOS TFT region, a p-type TFT region and a LDD region;

forming a semiconductive layer on the substrate;

patterning the semiconductive layer to form a first semiconductor island on the n-type MOS TFT region, a second semiconductor island on the p-type MOS TFT region, and the third semiconductor island on the LDD region respectively, wherein each of the second and third semiconductor island comprises a channel region and predetermined source and drain regions adjacent to the channel region and the first semiconductor islands comprise a channel region, predetermined lightly doped source and drain regions adjacent to the channel region, and predetermined source and drain regions adjacent to the predetermined lightly doped source and drain regions;

forming a patterned first mask layer to exposing the predetermined source and drain regions of the first and third semiconductor islands;

using the first mask layer as a mask to perform a heavily doped n-type ion implantation on the predetermined source and drain regions of the first and third semiconductor islands to form source/drain regions.

forming a gate oxide layer and a first conductor sequentially on the substrate and all semiconductor islands;

patterning the first conductive layer to form gate electrodes located on the gate oxide layer above the channel regions and source and drain electrodes located on the respective gate oxide layer adjacent to the channel region;

using the gate electrode above the first semiconductor island as a mask to perform a lightly doped n-type ion implantation on the predetermined lightly doped source and drain regions of the first semiconductor island to form lightly doped source and drain regions;

forming a patterned second mask layer to expose the surface of the gate oxide layer above the second semiconductor island;

performing a p-type ion implantation on the predetermined source and drain regions of the second semiconductor island to form source and drain regions with the gate electrode above the second semiconductor island acting as a mask;

forming a dielectric layer on the gate insulating layer, the gate electrodes, and the source and drain electrodes;

patterning the dielectric layer to form a plurality of contact holes via the dielectric layer and the gate insulating layer exposing part of the surface of source/drain regions and electrodes;

forming a patterned second conductive layer on predetermined parts of the dielectric layer to achieve the electrical connection of the LDD region and the electrical connection of the n-type MOS TFT and the p-type MOS TFT through the contact holes.

16. The method as claimed in claim 15, further comprising, before forming the semiconductive layer on the substrate, forming a buffer layer on the substrate.

17. The method as claimed in claim 15, wherein the semiconductive layer is a crystalline silicon layer.

18. The method as claimed in claim 17, wherein the method of forming a crystalline silicon layer comprises:

forming an amorphous silicon layer on the substrate; and

crystallizing the amorphous silicon layer to form the crystalline silicon layer by thermal application or excimer laser annealing (ELA) through a solid or liquid phase growing.

19. The method as claimed in claim 15, wherein the thickness of the gate insulating layer is 50 nm to 150 nm.

20. The method as claimed in claim 15, wherein the thickness of the dielectric layer is 300 nm to 3000 nm

21. The method as claimed in claim 15, wherein the plurality of contact holes is formed simultaneously by one photolithography step.