Input output control apparatus

• US 20050060476A1
• Filed: 08/11/2004
• Published: 03/17/2005
• Est. Priority Date: 08/12/2003
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Tamura, Takashi, Miyakoshi, Toshiyuki
• Granted Patent: US 7,752,375 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

The input output control device is provided with a plurality of fibre channel interface circuits and a protocol processing circuit capable of sequentially executing the protocol processing of each port, and is provided with a reception port identification register capable of identifying the port handling data to be received and a transmission port designation register designating the port handling data to be transmitted. In addition, it is possible to provide a controller using jointly the data buffers concerned with the plurality of ports. Control of a plurality of fibre channel interfaces with a low component count is possible, as is also the provision of an input output control device making an adequate capacity distribution with respect to the protocol processing between the plural fibre channel interfaces.

Claims

1. An input output control device controlling interfaces transmitting and receiving data in units of frames, wherein the input output control device comprises a plurality of interface control circuits controlling said interfaces independently for each port and a single protocol processing circuit carrying out the processing of transmitted and received data in each port via said plurality of interface control circuits.

2. The input output control device of claim 1, comprising a reception buffer control circuit storing, to a common received data buffer, the frame data received by said plurality of interface control circuits.

3. The input output control device of claim 2, wherein said reception buffer control circuit comprises a received data stack which, after said reception buffer control circuit has stored frame data from a certain interface control circuit to said received data buffer, stores buffer address information storing port identification information and frame data of the concerned interface control circuit.

4. The input output control device of claim 3, wherein said reception buffer control circuit comprises a reception port identification register sequentially reading out and storing the contents of said received data stack, as well as a reception buffer address information register, and, when said protocol processing circuit receives a processing request from said reception buffer control circuit, reads out and performs protocol processing of the contents of said reception port identification register and said reception buffer address information register.

5. The input output control device of claim 2, wherein each interface control circuit comprises a register which sets the received data buffer contents that can be used by the concerned port.

6. The input output control device of claim 1, comprising a transmission port designation register for the designation, by said protocol processing circuit, of the interface control circuit transmitting the frame data to be transmitted.

7. The input output control device of claim 6, comprising a common transmitted data buffer to which the frame data sent off to each interface control circuit is stored.

8. The input output control device of claim 7, comprising a transmission buffer address register for the setting, by said protocol processing circuit, of the buffer address information of the transmitted data buffer to which the frame data to be transmitted is stored.

9. The input output control device of claim 6, comprising a decoding circuit generating, when said protocol processing circuit has emitted a transmission instruction, a transmission instruction signal, from the contents of said transmission port designation register, to the designated interface control circuit.

10. The input output control device of claim 9, wherein said interface control circuit comprises a transmission stack reading out and storing the contents of said transmission buffer address register, after said interface control circuit has received said transmission instruction signal.

11. The input output control device of claim 10, wherein said interface control circuit sequentially reads out the transmission buffer address information stored in said transmission stack, reads out the corresponding transmission data from said transmitted data buffer, and comprises a frame generation circuit generating transmission frames.

12. The input output control device of claim 1, wherein said interfaces are fibre channel interfaces.

13. The input output control device of claim 12, comprising 2-Gbps fibre channel interfaces with four ports.

14. The input output control device of claim 12, comprising 2-Gbps fibre channel interfaces with four ports and a 10-Gbps fibre channel interface with one port and operating said 2-Gbps fibre channel interfaces and said 10-Gbps fibre channel interface in an exclusive manner.

15. The input output control device of claim 1, comprising a port identification means identifying which interface control circuit has received each frame, and a port designation means which sets the interface control circuit letting transmit the frame to be transmitted, both acting with respect to the plurality of frames received by said plurality of interface control circuits.

16. The input output control device of claim 1, wherein said plurality of interfaces are composed of physical interface media which differ from one another, and comprise a means for switching between a plurality of interfaces being of the same physical interface medium and an interface being of a physical interface medium that is different from the concerned physical interface medium.

17. A computer system, composed of a host, to which a central processing unit, a main storage device, and a bridge circuit are connected by means of a host bus controller, and a disk control device, to which a disk device and a bridge circuit are connected via a disk controller, wherein the computer system connects input output control devices of claim 12 respectively to the bridge circuit of said host and to the bridge circuit of said disk control device, and performs transmission and reception of data via fibre channel interfaces.