Memory device having a power down exit register

• US 20050060487A1
• Filed: 09/17/2004
• Published: 03/17/2005
• Est. Priority Date: 03/10/1998
• Status: Active Grant

• Current Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Original Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Davis, Paul G., Bystrom, Todd W., May, Bradley A.
• Granted Patent: US 7,574,616 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

Claims

1-24. -24. (cancelled)

25. A memory device comprising:

an interface to receive an instruction to exit a power down mode; and

a register to store a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command.

26. The memory device of claim 25, wherein, while in the power down mode, the memory device consumes less power than after exiting the power down mode.

27. The memory device of claim 25, further including an array of dynamic random access memory cells, wherein the command specifies an access to the array of dynamic random access memory cells.

28. The memory device of claim 27, further including a set of sense amplifiers, wherein the command is a row activate command, and wherein data corresponding to a row of the array of dynamic random access memory cells is transferred to the set of sense amplifiers in response to the row activate command.

29. The memory device of claim 28, further including a set of pins to receive a write command after receiving the row activate command, wherein the memory device inputs data to be written to the row of the array of dynamic random access memory cells in response to the write command.

30. The memory device of claim 28, further including a set of pins to receive a read command after receiving the row activate command, wherein the memory device outputs read data, selected from the data transferred to the set of sense amplifiers, in response to the read command.

31. The memory device of claim 30, further including a delay lock loop circuit to synchronize the output of the read data with an external clock signal.

32. The memory device of claim 30, further including a register to store a value that represents a number of clock cycles separating the row activate command and the read command.

33. The memory device of claim 25, further including a delay lock loop circuit to synchronize transfers of data, wherein the delay lock loop circuit reaches a predetermined state when exiting the power down mode.

34. The memory device of claim 33, wherein the predetermined state is based on when the delay lock loop circuit acquires synchronization with an external clock signal.

35. The memory device of claim 33, wherein the predetermined state is based on when the memory device is ready to receive the command.

36. The memory device of claim 33, wherein the delay lock loop circuit senses and tracks edges of the external clock signal to synchronize the transfers of the data.

37. The memory device of claim 25, wherein the period of time programmed in the register is based on information stored on a serial presence detect device, wherein the serial presence detect device is included with the memory device on a memory module.

38. A memory device comprising:

an array of memory cells;

a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode, wherein the command specifies an access to the array of memory cells; and

a delay lock loop circuit to synchronize data transfers using an external clock signal, wherein the delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

39. The memory device of claim 38, wherein the delay lock loop circuit reaches a predetermined state when exiting the power down mode, wherein the memory device is ready to receive the command upon reaching the predetermined state.

40. The memory device of claim 39, wherein the predetermined state is based on when the delay lock loop circuit acquires synchronization with the external clock signal

41. The memory device of claim 38, wherein, while in the power down mode, the memory device consumes less power than in a full power mode, wherein the memory device receives the command while in the full power mode.

42. The memory device of claim 38, wherein the register circuit includes:

a first register to store first information that pertains to the delay lock loop circuit; and

a second register to store second information that pertains to the delay locked loop circuit.

43. The memory device of claim 42, wherein:

the first information is coarse biasing information that is associated with a first period of time in which the delay lock loop circuit acquires synchronization with the external clock signal such that a limited functionality of the memory device is achieved; and

the second information is fine biasing information that is associated with a second period of time in which the delay locked loop acquires synchronization with the external clock signal such that a full functionality of the memory device is achieved.

44. The memory device of claim 43, wherein the period of time that elapses before receiving the command is an aggregate of the first period of time and the second period of time.

45. The memory device of claim 44, wherein the value is derived from the aggregate of the first period of time and the second period of time is derived by summing the first period of time, expressed as a first number of clock cycles of the external clock signal, with the second period of time, expressed as a second number of clock cycles of the external clock signal, wherein:

the first number of clock cycles is based on the first period of time divided by a period of the external clock signal; and

the second number of clock cycles is based on the second period of time divided by the period of the external clock signal.

46. The memory device of claim 38, wherein the memory device is in the power down mode during initialization of the memory device.

47. The memory device of claim 46, wherein the initialization is conducted in accordance with a first clock frequency and the memory device is operable in accordance with a second clock frequency during memory access operations, wherein the first clock frequency is lower than the second clock frequency.

48. The memory device of claim 46, wherein the memory device further includes an interface to receive an instruction to exit the power down mode.

49. A memory device comprising:

an array of memory cells;

a register circuit to store a value representative of a time at which the memory device is ready to receive a command when exiting from a power down mode, wherein the command specifies an access to the array of memory cells; and

a delay lock loop circuit to synchronize data transfers using an external clock signal, wherein the delay lock loop circuit reaches a predetermined state during exit from the power down mode, wherein the memory device is ready to receive the command upon reaching the predetermined state.

50. The memory device of claim 49, wherein the predetermined state is based on when the delay lock loop circuit acquires synchronization with the external clock signal.

51. The memory device of claim 49, wherein the predetermined state is based on when the delay locked loop achieves a predetermined synchronization with the external clock signal.

52. The memory device of claim 49, wherein, while in the power down mode, the memory device consumes less power than in a full power mode, wherein the memory device receives the command while in the full power mode.

53. The memory device of claim 49, wherein the memory device further includes an interface to receive an instruction to exit the power down mode.

54. The memory device of claim 49, wherein the value stored in the register circuit is based on information stored in a serial presence detect device, wherein the serial presence detect device is included, with the memory device, on a memory module.

55. A memory device comprising:

a clock receiver to receive an external clock signal;

an interface to receive an instruction to exit a power down mode, wherein, while in the power down mode, the memory device consumes less power than after exiting the power down mode;

a register circuit to store a value that is representative of a period of time that elapses before receiving a read command once the instruction to exit the power down mode has been received, wherein the read command instructs the memory device to output data; and

a delay lock loop circuit to synchronize data output in response to the read command, wherein the delay lock loop circuit establishes synchronization with an external clock signal during the period of time.

56. The memory device of claim 55, wherein the delay lock loop circuit reaches a predetermined state while exiting the power down mode, wherein the memory device is ready to receive the read command upon reaching the predetermined state.

57. The memory device of claim 55, wherein the predetermined state is based on when the delay locked loop circuit establishes synchronization with the external clock signal.

58. The memory device of claim 55, wherein, while in the power down mode, the memory device consumes less power than in a full power mode, wherein the memory device receives the read command while in the full power mode.

59. The memory device of claim 58, wherein the register circuit further includes:

a first register to store coarse biasing information that is associated with a first period of time during which the delay lock loop circuit acquires the external clock signal such that a limited functionality of the memory device is achieved; and

a second register to store fine biasing information that is associated with a second period of time during which the delay locked loop circuit acquires the external clock signal such that a full functionality of the memory device is achieved.

60. The memory device of claim 59, wherein the period of time that elapses before receiving the read command is an aggregate of the first period of time and the second period of time.

61. The memory device of claim 55, wherein the memory device is in the power down mode during initialization of the memory device.

62. The memory device of claim 61, wherein the initialization is conducted in accordance with a first clock frequency, and wherein the memory device is operable in accordance with a second clock frequency during memory access operations, wherein the first clock frequency is lower than the second clock frequency.

63. The memory device of claim 55, wherein the value is selected based on information stored in a serial presence detect device, wherein the serial presence detect device is included, with the memory device, on a memory module.

64. The memory device of claim 63, wherein the information indicates a period of time for an exit from the power down mode, wherein the value is selected by dividing the period of time by a period of the external clock signal to select the value in terms of clock cycles of the external clock signal.

65. The memory device of claim 64, wherein the value is selected and rounded to a next whole number if a fractional number of clock cycles results when dividing the period of time by the period of the external clock signal.

66. A method of operation in a memory device, the method comprising:

step for receiving an instruction to exit a power down mode, wherein, while in the power down mode, the memory device consumes less power than after exiting the power down mode; and

step for storing a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command.