System and method for on-board timing margin testing of memory modules
First Claim
1. A memory module, comprising:
- a plurality of memory devices; and
a memory hub, comprising;
a link interface for receiving memory requests for access to at least one of the memory devices;
memory device interface coupled to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device; and
a self-test module coupled to at least one of the memory devices, the self-test module being operable to couple a series of corresponding first and second signals to the at least one memory device and to alter the relative timing between when some of the corresponding first and second signals in the series are coupled to the at least one memory device over a range, the self-test module further receiving output signals from the at least one memory device and determining based on the received output signals whether the at least one memory device properly responded to the series of first and second signals.
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Accused Products
Abstract
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.
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Citations
50 Claims
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1. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a link interface for receiving memory requests for access to at least one of the memory devices;
memory device interface coupled to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device; and
a self-test module coupled to at least one of the memory devices, the self-test module being operable to couple a series of corresponding first and second signals to the at least one memory device and to alter the relative timing between when some of the corresponding first and second signals in the series are coupled to the at least one memory device over a range, the self-test module further receiving output signals from the at least one memory device and determining based on the received output signals whether the at least one memory device properly responded to the series of first and second signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a link interface for receiving memory requests for access to at least one of the memory devices;
memory device interface coupled to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device; and
a self-test module coupled to at least one of the memory devices, the self-test module being operable to receive first and second signals from the at least one memory device, the self-test module being operable to alter the relative timing between when some of the corresponding first and second signals in the series are coupled from the at least one memory device over a range and to evaluate the operation of the least one memory device based on the first and second signals. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A memory module, comprising:
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a plurality of synchronous memory devices; and
a memory hub, comprising;
a link interface for receiving memory requests for access to at least one of the memory devices;
memory device interface coupled to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device; and
a variable frequency clock generator producing and coupling to the at least one memory device a clock signal having a frequency corresponding to a frequency control signal; and
a self-test module coupled to at least one of the memory devices, the self-test module being operable to generate the frequency control signal so that the frequency of the clock signal varies over a range, the self-test module further being operable couple a series of first input signals to the at least one memory device and to receive output signals from the at least one memory device and determining based on the received output signals whether the at least one memory device properly responded to the series of first signals as the frequency of the clock signal is varied. - View Dependent Claims (20, 21, 22)
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23. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a memory module coupled to the system memory port of the system controller, the memory module comprising;
a plurality of memory devices; and
a memory hub, comprising;
a link interface coupled to the system memory port for receiving memory requests for access to at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device; and
a self-test module coupled to at least one of the memory devices, the self-test module being operable to couple a series of corresponding first and second signals to the at least one memory device and to alter the relative timing between when some of the corresponding first and second signals in the series are coupled to the at least one memory device over a range, the self-test module further receiving output signals from the at least one memory device and determining based on the received output signals whether the at least one memory device properly responded to the series of first and second signals. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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32. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a memory module coupled to the system memory port of the system controller, the memory module comprising;
a plurality of synchronous memory devices; and
a memory hub, comprising;
a link interface for receiving memory requests for access to at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface coupling write memory requests and write data to the memory devices, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device; and
a variable frequency clock generator producing and coupling to the at least one memory device a clock signal having a frequency corresponding to a frequency control signal; and
a self-test module coupled to at least one of the memory devices, the self-test module being operable to generate the frequency control signal so that the frequency of the clock signal varies over a range, the self-test module further being operable couple a series of first input signals to the at least one memory device and to receive output signals from the at least one memory device and determining based on the received output signals whether the at least one memory device properly responded to the series of first signals as the frequency of the clock signal is varied. - View Dependent Claims (33, 34, 35)
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36. A method for performing signal timing testing on memory system having a memory hub coupled to a plurality of memory devices, the method comprising:
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generating testing signals in the memory hub;
coupling the testing signals from the memory hub to the memory devices while varying the relative timing between when the testing signals are applied to the memory devices generating output signals in the memory devices resulting from the testing signals;
coupling the output signals from the memory devices to the memory hub;
evaluating the output signals in the memory hub to determine if the memory devices properly responded to the test signals. - View Dependent Claims (37, 38, 39, 40, 41)
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42. A method for performing signal timing testing on memory system having a memory hub coupled to a plurality of memory devices, the method comprising:
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in the memory hub, generating write data and a data strobe signal for each of a plurality of write memory operations;
storing the write data in the memory hub;
coupling the write data and the data strobe signal for each of the plurality of write memory operations from the memory hub to the memory devices while altering the relative timing between the write data and the data strobe signal in at least some of the write memory operations;
in the memory devices, storing the write data coupled from the memory hub;
reading the write data stored in the memory devices by coupling read data from the memory devices to the memory hub in each of a plurality of read data operations; and
in the memory hub, comparing the read data coupled from the memory devices to the write data coupled to the memory devices. - View Dependent Claims (43)
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44. A method for performing signal timing testing on memory system having a memory hub coupled to a plurality of memory devices, the method comprising:
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in the memory hub, generating a memory command and a clock signal for each of a plurality of memory operations;
coupling the memory command and the clock signal for each of the plurality of memory operations from the memory hub to the memory devices while altering the relative timing between the memory command and the clock signal in at least some of the memory operations;
in the memory devices, performing a memory operation for each of the plurality of memory commands;
reading the data from the memory devices by coupling read data from the memory devices to the memory hub in each of a plurality of read data operations; and
in the memory hub, determining if the memory devices properly performed the memory operations corresponding to the memory commands based on the read data.
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45. A method for performing signal timing testing on memory system having a memory hub coupled to a plurality of memory devices, the method comprising:
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in the memory hub, generating a clock signal having a variable frequency;
coupling test signals and the clock signal for each of a plurality of memory operations from the memory hub to the memory devices while altering the frequency of the clock signal in at least some of the memory operations;
in the memory devices, responding to the test signals coupled from the memory hub;
reading data stored in the memory devices by coupling read data from the memory devices to the memory hub in each of a plurality of read data operations; and
in the memory hub, determining from the read data coupled from the memory devices whether the memory devices properly performed the memory operations. - View Dependent Claims (46, 47, 48, 49, 50)
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Specification