Integrated test-on-chip system and method and apparatus for manufacturing and operating same

• US 20050060627A1
• Filed: 08/02/2004
• Published: 03/17/2005
• Est. Priority Date: 08/01/2003
• Status: Active Grant

• Current Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Original Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Inventors: Maltseff, Paul A., Payne, Ronald D.
• Granted Patent: US 7,249,302 B2
• Time in Patent Office: Days
• US Class Current: 714/733
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT

Abstract

A microchip system comprises a self check subsystem operable to perform a self test of at least one subsystem of the microchip system, and/or on the interoperability of subsystems. An antenna and a communications subsystem wirelessly transmit self check information from the microchip system. The communications subsystem may also receive information, data or instructions from an off-chip system or device. Self check tests may occur during manufacture of the microchip system and/or during operation. The microchip system may comprise a passive power subsystem coupled to an antenna to receive power in the form of an electromagnetic field, and which provides electrical power derived therefrom to at least one other subsystem of the microchip system.

Claims

1. A microchip system, comprising:

a substrate;

a control subsystem carried by the substrate and operable to perform a self test of at least one subsystem of the microchip system;

an antenna; and

a communications subsystem carried by the substrate, the communications subsystem coupled to the antenna and operable to wirelessly transmit self check information resulting from the self test of at least one subsystem from the microchip system.

2. The microchip system of claim 1 wherein the control subsystem is operable to perform a self test on the communications subsystem.

3. The microchip system of claim 1, further comprising:

a passive power subsystem carried by the substrate and coupled to the antenna to receive power thereby in the form of an electromagnetic field and coupled to provide power to at least one other subsystem of the microchip system.

4. The microchip system of claim 1, further comprising:

a power storage device carried by the substrate and coupled to provide power to at least one subsystem of the microchip system.

5. The microchip system of claim 1, further comprising:

at least a first micro-electrical-mechanical structure formed on at least a portion of the substrate, the first micro-electrical-mechanical structure operable to perform at least one physical action on at least one physical work product, wherein the control subsystem is operable to perform a self test of the first micro-electrical-mechanical structure.

6. The microchip system of claim 1, further comprising:

at least a first subsystem of an integrated circuit system formed on the substrate, wherein the control subsystem is operable to perform a self test of the first subsystem of the integrated circuit system.

7. The microchip system of claim 6, further comprising:

at least a second subsystem of the integrated circuit system formed on the substrate, wherein the control subsystem is configured to perform a self check of the first subsystem of the integrated circuit after the first subsystem of the integrated circuit is formed on the substrate and before the second subsystem of the integrated circuit system is formed on the substrate, and to perform a self check of the second subsystem of the integrated circuit after the second subsystem of the integrated circuit is formed on the substrate.

8. The microchip system of claim 1 wherein the control subsystem is configured to perform a self check of each of a number of the subsystems after each of at least one manufacturing operation is performed in manufacturing the microchip system.

9. The microchip system of claim 1 wherein the control subsystem is configured to perform a self check of each of a number of the subsystems after each of at least two manufacturing operations is performed in manufacturing the microchip system.

10. The microchip system of claim 1 wherein control subsystem comprises a memory coupled to the antenna to store a self check routine received via the antenna.

11. The microchip system of claim 1 wherein the antenna is carried by the substrate.

12. The microchip system of claim 1, further comprising:

a communications port, wherein the antenna is communicatively coupled to the communications port and the antenna is not carried by the substrate.

13. A method of operating a microchip system;

comprising;

performing at least a first self check test of at least one subsystem at a first time with a control subsystem carried by the substrate; and

wirelessly transmitting results of the first self check test from the microchip system.

14. The method of claim 13, comprising:

forming the control subsystem on the substrate; and

performing a self check test of the control subsystem after forming the control subsystem on the substrate.

15. The method of claim 13, comprising:

forming the control subsystem on the substrate;

forming a communications subsystem on the substrate; and

performing a self check test of the communications subsystem with the control subsystem.

16. The method of claim 13, comprising:

forming the control subsystem on the substrate;

forming a communications subsystem on the substrate;

forming an antenna on the substrate the antenna communicatingly coupled to the communications subsystem; and

performing a self check test of the communications subsystem with the control subsystem after forming the communications subsystem and the antenna on the substrate.

17. The method of claim 13, comprising:

locating a communications subsystem on the substrate; and

performing a self check test of the communications subsystem with the control subsystem after locating the communications subsystem on the substrate.

18. The method of claim 17, comprising:

coupling an off substrate antenna to the communications system.

19. The method of claim 13, comprising:

forming a first subsystem of an integrated circuit system on the substrate; and

performing a self check test of the first subsystem of the integrated circuit system with a control subsystem carried by the substrate after forming the first subsystem of the integrated circuit system on the substrate.

20. The method of claim 19, comprising:

terminating manufacture of the microchip system before forming a second subsystem of the integrated circuit system on the substrate if the first subsystem of the integrated circuit system is faulty.

21. The method of claim 19, comprising:

forming a second subsystem of an integrated circuit system on the substrate after performing a self check test of the first subsystem of the integrated circuit system, if the first subsystem of the integrated circuit system is not faulty; and

performing a self check test of the second subsystem of the integrated circuit system with the control subsystem after forming the second subsystem of the integrated circuit system on the substrate.

22. The method of claim 21, comprising:

performing a self check test of an interoperability of the first and the second subsystems of the integrated circuit system after forming the first and the second subsystems of the integrated circuit system on the substrate.

23. The method of claim 22, comprising:

forming a third subsystem of an integrated circuit system on the substrate after performing a self check test of the second subsystem of the integrated circuit system, if the first and the second subsystems of the integrated circuit system is not faulty and if the interoperability of the first and the second subsystems of the integrated circuit subsystem is not faulty; and

performing a self check test of the third subsystem of the integrated circuit system with the control subsystem after forming the third subsystem of the integrated circuit system on the substrate.

24. The method of claim 21, comprising:

forming a third subsystem of an integrated circuit system on the substrate after performing a self check test of the second subsystem of the integrated circuit system, if the first and the second subsystems of the integrated circuit system is not faulty; and

performing a self check test of the third subsystem of the integrated circuit system with the control subsystem after forming the third subsystem of the integrated circuit system on the substrate.

25. The method of claim 19, comprising:

forming an interface subsystem on the substrate, the interface subsystem couplable to interface between a control subsystem carried by the substrate and at least a portion of the integrated circuit system; and

performing a self check test of the interface subsystem with the control subsystem after forming the interface subsystem on the substrate.

26. The method of claim 13, comprising:

forming at least one micro-electrical-mechanical structure on the substrate; and

performing a self test of the at least one micro-electrical-mechanical structure after forming the at least one micro-electrical-mechanical structure on the substrate.

27. The method of claim 26, comprising:

forming an interface subsystem on the substrate, the interface subsystem couplable to provide an interface between a control subsystem carried by the substrate and the at least one micro-electrical-mechanical structure of the substrate; and

performing a self check test of the interface subsystem with the control subsystem after forming the interface subsystem on the substrate.

28. The method of claim 13, comprising:

receiving an electromagnetic field at an antenna;

converting the electromagnetic field into electrical power; and

providing the electrical power to at least one subsystem of the microchip system.

29. The method of claim 28 wherein providing the electrical power to at least one subsystem of the microchip system comprises supplying a portion of the electrical power to the control subsystem.

30. The method of claim 13 wherein performing at least a first self check test comprises performing a respective self check test after forming each of a plurality of subsystems on the substrate.

31. The method of claim 13 wherein performing at least a first self check test occurs between a start and a finish of a manufacturing of the microchip system.

32. The method of claim 13 wherein performing at least a first self check test occurs in an operational environment after completion of manufacturing of the microchip system.

33. The method of claim 13, further comprising:

forming a replacement subsystem on the substrate for the at least one subsystem if the at least one subsystem is faulty.

34. The method of claim 13, further comprising:

forming a replacement subsystem on the substrate for the at least one subsystem of the integrated circuit system if the at least one subsystem of the integrated circuit system is faulty.