Method to prevent damage to probe card

• US 20050060882A1
• Filed: 11/08/2004
• Published: 03/24/2005
• Est. Priority Date: 06/25/2001
• Status: Abandoned Application

• Current Assignee: Phillip E. Byrd
• Original Assignee: Phillip E. Byrd
• Inventors: Byrd, Phillip E.
• Application Number:
  US10/984,381
• Publication Number:
  US 20050060882A1
• Time in Patent Office: Days
• US Class Current: 29/832
• CPC Class Codes: G01R 1/06766 Input circuits therefor
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H05K 1/0293 Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 1/167 incorporating printed resistors
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/10053 Switch
• CPC Class Codes: H05K 2201/10181 Fuse
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49005 Acoustic transducer
• CPC Class Codes: Y10T 29/49107 Fuse making
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49139 by inserting component lead or terminal into base aperture
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

Method of forming probe cards is configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.

Claims

1. A method of forming a probe card comprising:

providing a substrate having a first surface and a second surface;

disposing a plurality of conductive traces adjacent at least one of the first surface and the second surface;

providing a plurality probe elements in electrical communication with the plurality of conductive traces; and

providing a plurality of fuse elements in respective electrical communication with at least some of the plurality of conductive traces, at least some of the plurality of fuse elements disposed immediately adjacent at least one of the first surface and the second surface.

2. The method of claim 1, wherein providing a plurality of fuse elements comprises providing a fuse element of the plurality of fuse elements in respective electrical communication with substantially each of the plurality of conductive traces.

3. The method of claim 1, wherein providing a plurality of fuse elements comprises providing at least one fuse element of the plurality of fuse elements configured to be replaceable or repairable after being tripped.

4. The method of claim 3, further comprising constructing at least some of the plurality of conductive traces and at least some of the plurality of fuse elements at substantially the same time and by a single deposition process.

5. The method of claim 3, further comprising providing a plurality of test contacts adjacent the at least one of the first surface and the second surface of the substrate, at least some of the plurality of test contacts in electrical communication with respective conductive traces of the plurality of conductive traces, and further comprising forming each of the plurality of conductive traces, the plurality of fuse elements, and the plurality of test contacts of the same materials.

6. The method of claim 1, wherein providing a plurality of fuse elements comprises inserting at least one of the plurality of fuse elements in through-hole portions configured in the at least one of the first surface and the second surface of the substrate.

7. The method of claim 1, wherein providing a plurality of fuse elements comprises providing at least one of the plurality of fuse elements configured as a dual in-line pin header fuse.

8. The method of claim 1, wherein providing a plurality of fuse elements comprises providing at least one of the plurality of fuse elements configured as a dual in-line socket fuse.

9. The method of claim 1, wherein at least one fuse element of the plurality of fuse elements is configured to be self-resetting after being tripped.

10. The method of claim 9, wherein the at least one fuse element is configured as a PPTC fuse.

11. The method of claim 9, wherein the at least one fuse element is configured as a bimetallic switch.

12. A method of fabricating a probe card comprising:

providing a probe card substrate;

providing a plurality of conductive traces adjacent a surface of the probe card substrate;

providing a plurality of probe elements in electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements configured for supplying a test signal to at least one semiconductor die; and

providing at least one repairable or replaceable fuse component in electrical communication with at least one of the plurality of conductive traces.

13. The method of claim 12, further comprising providing a test contact in electrical communication with at least one conductive trace of the plurality of conductive traces, and further comprising providing a pogo pin in electrical communication with the test contact, wherein the at least one repairable or replaceable fuse component is configured as a portion of the pogo pin.

14. The method of claim 12, wherein providing a plurality of probe elements comprises providing a plurality of probe elements in a configuration adapted to be temporarily electrically coupled with a semiconductor wafer having a plurality of electrical contacts thereon.

15. The method of claim 14, wherein providing a plurality of probe elements comprises arranging conductive tips of the plurality of probe elements in a mirror image of a pattern of the plurality of electrical contacts on the semiconductor wafer.

16. The method of claim 14, further comprising providing a probe card substrate with a coefficient of thermal expansion which substantially matches a coefficient of thermal expansion of the semiconductor wafer.

17. The method of claim 12, wherein providing at least one repairable or replaceable fuse component comprises providing an active fuse.

18. The method of claim 12, wherein providing at least one repairable or replaceable fuse component comprises providing a passive fuse.

19. The method of claim 18, further comprising providing a plurality of test contacts in electrical communication with respective conductive traces of the plurality of conductive traces, and wherein providing a passive fuse comprises providing a passive fuse configured as a cutout portion of at least one test contact of the plurality of test contacts.

20. A method of forming a probe card using a substrate having a first surface and a second surface comprising:

disposing a plurality of conductive traces adjacent at least one of the first surface and the second surface;

placing a plurality of probe elements in electrical communication with the plurality of conductive traces; and

placing a plurality of fuse elements in respective electrical communication with at least some of the plurality of conductive traces, at least some of the plurality of fuse elements disposed immediately adjacent at least one of the first surface and the second surface.

21. The method of claim 20, wherein placing a plurality of fuse elements comprises placing a fuse element of the plurality of fuse elements in respective electrical communication with substantially each of the plurality of conductive traces.

22. The method of claim 20, wherein placing a plurality of fuse elements comprises placing at least one fuse element of the plurality of fuse elements configured to be replaceable or repairable after being tripped.

23. The method of claim 22, further comprising constructing at least some of the plurality of conductive traces and at least some of the plurality of fuse elements at substantially the same time and by a single deposition process.

24. The method of claim 22, further comprising providing a plurality of test contacts adjacent the at least one of the first surface and the second surface of the substrate, at least some of the plurality of test contacts in electrical communication with respective conductive traces of the plurality of conductive traces, and further comprising forming each of the plurality of conductive traces, the plurality of fuse elements, and the plurality of test contacts of the same materials.

25. The method of claim 20, wherein placing a plurality of fuse elements comprises inserting at least one of the plurality of fuse elements in through-hole portions configured in the at least one of the first surface and the second surface of the substrate.

26. The method of claim 20, wherein placing a plurality of fuse elements comprises placing at least one of the plurality of fuse elements configured as a dual in-line pin header fuse.

27. The method of claim 20, wherein placing a plurality of fuse elements comprises placing at least one of the plurality of fuse elements configured as a dual in-line socket fuse.

28. The method of claim 20, wherein at least one fuse element of the plurality of fuse elements comprises a self-resetting fuse element after being tripped.

29. The method of claim 28, wherein the at least one fuse element comprises a PPTC fuse.

30. The method of claim 28, wherein the at least one fuse element comprises a bimetallic switch.

31. A method of fabricating a probe card using a probe card substrate comprising:

forming a plurality of conductive traces adjacent a surface of the probe card substrate;

providing a plurality of probe elements in electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements configured for supplying a test signal to at least one semiconductor die; and

providing at least one repairable or replaceable fuse component in electrical communication with at least one of the plurality of conductive traces.

32. The method of claim 31, further comprising providing a test contact in electrical communication with at least one conductive trace of the plurality of conductive traces, and further comprising providing a pogo pin in electrical communication with the test contact, wherein the at least one repairable or replaceable fuse component is configured as a portion of the pogo pin.

33. The method of claim 31, wherein providing a plurality of probe elements comprises providing a plurality of probe elements in a configuration adapted to be temporarily electrically coupled with a semiconductor wafer having a plurality of electrical contacts thereon.

34. The method of claim 33, wherein providing a plurality of probe elements comprises arranging conductive tips of the plurality of probe elements in a mirror image of a pattern of the plurality of electrical contacts on the semiconductor wafer.

35. The method of claim 33, further comprising providing a probe card substrate with a coefficient of thermal expansion which substantially matches a coefficient of thermal expansion of the semiconductor wafer.

36. The method of claim 31, wherein providing at least one repairable or replaceable fuse component comprises providing an active fuse.

37. The method of claim 31, wherein providing at least one repairable or replaceable fuse component comprises providing a passive fuse.

38. The method of claim 37, further comprising providing a plurality of test contacts in electrical communication with respective conductive traces of the plurality of conductive traces, and wherein providing a passive fuse comprises providing a passive fuse configured as a cutout portion of at least one test contact of the plurality of test contacts.

39. A method of fabricating a probe card using a probe card substrate comprising:

forming a plurality of conductive traces adjacent a surface of the probe card substrate;

installing a plurality of probe elements in electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements configured for supplying a test signal to at least one semiconductor die; and

providing at least one repairable or replaceable fuse component in electrical communication with at least one of the plurality of conductive traces.

40. The method of claim 39, further comprising providing a test contact in electrical communication with at least one conductive trace of the plurality of conductive traces, and further comprising providing a pogo pin in electrical communication with the test contact, wherein the at least one repairable or replaceable fuse component is configured as a portion of the pogo pin.

41. The method of claim 39, wherein installing a plurality of probe elements comprises installing a plurality of probe elements in a configuration adapted to be temporarily electrically coupled with a semiconductor wafer having a plurality of electrical contacts thereon.

42. The method of claim 41, wherein installing a plurality of probe elements comprises arranging conductive tips of the plurality of probe elements in a mirror image of a pattern of the plurality of electrical contacts on the semiconductor wafer.

43. The method of claim 41, further comprising installing a probe card substrate with a coefficient of thermal expansion which substantially matches a coefficient of thermal expansion of the semiconductor wafer.

44. The method of claim 41, wherein providing at least one repairable or replaceable fuse component comprises providing an active fuse.

45. The method of claim 41, wherein providing at least one repairable or replaceable fuse component comprises providing a passive fuse.

46. The method of claim 45, further comprising providing a plurality of test contacts in electrical communication with respective conductive traces of the plurality of conductive traces, and wherein providing a passive fuse comprises providing a passive fuse configured as a cutout portion of at least one test contact of the plurality of test contacts.

47. A method of fabricating a probe card using a probe card substrate comprising:

forming a plurality of conductive traces adjacent a surface of the probe card substrate;

forming a plurality of probe elements in electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements configured for supplying a test signal to at least one semiconductor die; and

providing at least one repairable or replaceable fuse component in electrical communication with at least one of the plurality of conductive traces.

48. The method of claim 47, further comprising providing a test contact in electrical communication with at least one conductive trace of the plurality of conductive traces, and further comprising providing a pogo pin in electrical communication with the test contact, wherein the at least one repairable or replaceable fuse component is configured as a portion of the pogo pin.

49. The method of claim 47, wherein forming a plurality of probe elements comprises forming a plurality of probe elements in a configuration adapted to be temporarily electrically coupled with a semiconductor wafer having a plurality of electrical contacts thereon.

50. The method of claim 49, wherein forming a plurality of probe elements comprises arranging conductive tips of the plurality of probe elements in a mirror image of a pattern of the plurality of electrical contacts on the semiconductor wafer.

51. The method of claim 49, further comprising forming a probe card substrate with a coefficient of thermal expansion which substantially matches a coefficient of thermal expansion of the semiconductor wafer.

52. The method of claim 47, wherein providing at least one repairable or replaceable fuse component comprises providing an active fuse.

53. The method of claim 47, wherein providing at least one repairable or replaceable fuse component comprises providing a passive fuse.

54. The method of claim 47, further comprising providing a plurality of test contacts in electrical communication with respective conductive traces of the plurality of conductive traces, and wherein providing a passive fuse comprises providing a passive fuse configured as a cutout portion of at least one test contact of the plurality of test contacts.