Static random access memory

• US 20050062071A1
• Filed: 08/03/2004
• Published: 03/24/2005
• Est. Priority Date: 09/24/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Uchida, Ken, Matsuzawa, Kazuya, Nakauchi, Takahiro
• Granted Patent: US 7,057,302 B2
• Time in Patent Office: Days
• US Class Current: 257/222
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode. The gate electrode shared by the first and second complementary field-effect transistors is connected to the common drain region of the mutually opposing complementary field-effect transistors, and the static random access memory has superior resistance to software errors.

Claims

1. Static random access memory having a first complementary field-effect transistor, a first transfer gate, a second complementary field-effect transistor, and a second transfer gate, wherein

the first complementary field-effect transistor has a first field-effect transistor of electron conduction type and a first field-effect transistor of positive hole conduction type;

the second complementary field-effect transistor has a second field-effect transistor of electron conduction type and a second field-effect transistor of positive hole conduction type;

the first field-effect transistor of electron conduction type has a first drain region constituting a Schottky junction with a semiconductor substrate and a gate electrode formed on the semiconductor substrate;

the first field-effect transistor of positive hole conduction type shares the first drain region in conjunction with the first field-effect transistor of electron conduction type and has a gate electrode which is shared by the first field-effect transistor of electron conduction type and provided on the semiconductor substrate;

the first transfer gate is formed from a field-effect transistor which shares the first drain region with the first complementary field-effect transistor;

the second field-effect transistor of electron conduction type has a second drain region constituting a Schottky junction with the semiconductor substrate and a gate electrode formed on the semiconductor substrate;

the second field-effect transistor of positive hole conduction type shares the second drain region in conjunction with the second field-effect transistor of electron conduction type and has a gate electrode which is shared by the second field-effect transistor of electron conduction type and provided on the semiconductor substrate;

the second transfer gate is formed from a field-effect transistor which shares the second drain region with the second complementary field-effect transistor;

the common gate electrode of the first complementary field-effect transistor is connected to the second drain region; and

the common gate electrode of the second complementary field-effect transistor is connected to the first drain region.

3. The static random access memory according to claim 1,

wherein the first and second drain regions are formed from an integral metallic material film.

5. The static random access memory according to claim 1,

wherein a work function of a metallic material of the first and second drain regions is higher than an energy value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of positive hole conduction type formed in the semiconductor substrate.

7. The static random access memory according to claim 3,

wherein a work function of a metallic material of the first and second drain regions is higher than an energy value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of positive hole conduction type formed in the semiconductor substrate.

9. The static random access memory according to claim 1,

wherein a work function of a metallic material of the first and second drain regions is lower than an energy value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of electron conduction type formed in the semiconductor substrate.

11. The static random access memory according to claim 3,

wherein a work function of a metallic material of the first and second drain regions is lower than an energy value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of electron conduction type formed in the semiconductor substrate.

2. Static random access memory having a first complementary field-effect transistor, a first transfer gate, a second complementary field-effect transistor, and a second transfer gate, wherein

the first complementary field-effect transistor has a first field-effect transistor of electron conduction type, a first field-effect transistor of positive hole conduction type, and a first interconnection;

the second complementary field-effect transistor has a second field-effect transistor of electron conduction type, a second field-effect transistor of positive hole conduction type, and a second interconnection;

the first field-effect transistor of electron conduction type has a first drain region constituting a Schottky junction with a semiconductor substrate and a gate electrode formed on the semiconductor substrate;

the first field-effect transistor of positive hole conduction type shares the first drain region in conjunction with the first field-effect transistor of electron conduction type and has a gate electrode which is shared by the first field-effect transistor of electron conduction type;

the first transfer gate is formed from a field-effect transistor which shares the first drain region with the first complementary field-effect transistor;

the first interconnection is formed in the first drain region by way of a dielectric layer and connects the gate electrode of the first field-effect transistor of electron conduction type to the gate electrode of the first field-effect transistor of positive hole conduction type;

the second field-effect transistor of electron conduction type has a second drain region constituting a Schottky junction with the semiconductor substrate and a gate electrode formed on the semiconductor substrate;

the second field-effect transistor of positive hole conduction type shares the second drain region in conjunction with the second field-effect transistor of electron conduction type and has a gate electrode which is shared by the second field-effect transistor of electron conduction type;

the second transfer gate is formed from a field-effect transistor which shares the second drain region with the second complementary field-effect transistor;

the second interconnection is formed in the second drain region by way of a dielectric layer and connects the gate electrode of the second field-effect transistor of electron conduction type to the gate electrode of the second field-effect transistor of positive hole conduction type;

a common gate electrode of the first complementary field-effect transistor is connected to the second drain region; and

a common gate electrode of the second complementary field-effect transistor is connected to the first drain region.

4. The static random access memory according to claim 2,

wherein the first and second drain regions are formed from an integral metallic material film.

6. The static random access memory according to claim 2,

wherein a work function of a metallic material of the first and second drain regions is higher than an energy value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of positive hole conduction type formed in the semiconductor substrate.

8. The static random access memory according to claim 4,

wherein a work function of a metallic material of the first and second drain regions is higher than an energy value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of positive hole conduction type formed in the semiconductor substrate.

10. The static random access memory according to claim 2,

wherein a work function of a metallic material of the first and second drain regions is lower than an energy value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of electron conduction type formed in the semiconductor substrate.

12. The static random access memory according to claim 4,

wherein a work function of a metallic material of the first and second drain regions is lower than an energy, value at the center of an energy band gap of an intrinsic semiconductor, and the first and second drain regions are covered with a semiconductor region of electron conduction type formed in the semiconductor substrate.