Trench MOSFET device with polycrystalline silicon source contact structure

• US 20050062075A1
• Filed: 11/08/2004
• Published: 03/24/2005
• Est. Priority Date: 11/20/2001
• Status: Active Grant

• Current Assignee: Fwu-Iuan Hshieh, John E. Amato, Koon Chong So, Yan Man Tsui
• Original Assignee: Fwu-Iuan Hshieh, John E. Amato, Koon Chong So, Yan Man Tsui
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man, Amato, John E.
• Granted Patent: US 7,015,125 B2
• Time in Patent Office: Days
• US Class Current: 257/222
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

Claims

1. A method of forming a trench MOSFET transistor device comprising:

providing a silicon substrate of a first conductivity type;

depositing a silicon epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;

etching a trench extending into said epitaxial layer from an upper surface of said epitaxial layer;

forming an insulating layer that lines at least a portion of said trench;

forming a conductive region within said trench and adjacent said insulating layer;

forming a body region of a second conductivity type within an upper portion of said epitaxial layer and adjacent said trench;

forming a source region of said first conductivity type within an upper portion of said body region and adjacent said trench;

forming an upper region of second conductivity type within an upper portion of said body region and adjacent said source region, said upper region having a higher majority carrier concentration than said body region; and

forming a source contact region on said epitaxial layer upper surface, said source contact region comprising (a) a doped polycrystalline silicon contact region in electrical contact with said source region and (b) a metal contact region adjacent said doped polycrystalline silicon contact region and in electrical contact with said source region and with said upper region.

2. The method of claim 1, further comprising forming an insulating region over said conductive region, said insulating region extending above said epitaxial layer upper surface.

3. The method of claim 2, wherein insulating region is a borophosphosilicate glass region.

4. The method of claim 2, wherein said source contact region is formed by a process comprising:

(a) providing a layer of doped polycrystalline silicon over said insulating region and said epitaxial layer upper surface;

(b) etching said layer of doped polycrystalline silicon until a portion of said epitaxial layer upper surface is exposed and a portion of said doped polycrystalline silicon remains adjacent said insulating region, and (c) depositing a metal layer over said insulating region, said epitaxial layer upper surface, and said remaining portion of said doped polycrystalline silicon adjacent said insulating region.

5. The method of claim 4, wherein said layer of doped polycrystalline silicon layer is etched by reactive ion etching.