Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same

• US 20050062109A1
• Filed: 09/20/2004
• Published: 03/24/2005
• Est. Priority Date: 09/19/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Shin-Ae, Kim, Sung-Min, Cho, Hye-Jin, Park, Dong-Gun, Yun, Eun-Jung
• Granted Patent: US 7,129,541 B2
• Time in Patent Office: Days
• US Class Current: 257/397
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field effect transistor on an active region of a semiconductor substrate includes a vertically protruding thin-body portion of the semiconductor substrate and a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate. The transistor further includes an insulating layer surrounding an upper portion of the vertically oriented gate electrode and a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode. Accordingly, a T-shaped gate electrode is defined having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.

Claims

1. A field effect transistor on an active region of a semiconductor substrate, comprising:

a vertically protruding thin-body portion of the semiconductor substrate; and

a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate.

2. The transistor of claim 1, further comprising:

an insulating layer surrounding an upper portion of the vertically oriented gate electrode; and

a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode.

3. The transistor of claim 2, wherein the vertically oriented gate electrode comprises silicide, and wherein the laterally oriented gate electrode comprises one of polysilicon, metal, and metal silicide.

4. The transistor of claim 2, wherein the laterally oriented gate electrode has a width that is greater than a width of the vertically oriented gate electrode.

5. The transistor of claim 2, further comprising spacers surrounding the upper portion of the vertically oriented gate electrode between the vertically oriented gate electrode and the insulating layer.

6. The transistor of claim 1, further comprising a lower insulating layer inside the cavity between a bottom portion of the vertically oriented gate electrode and the substrate.

7. The transistor of claim 1, wherein the vertically oriented gate electrode has a lower portion inside the cavity and an upper portion outside the cavity, wherein the upper portion has a width greater than a width of the lower portion.

8. A field effect transistor in a non-volatile EPROM, comprising:

a T-shaped gate electrode having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.

9. The transistor of claim 8, wherein the T-shaped gate electrode is a first T-shaped gate electrode and the cavity is a first cavity, and further comprising a second T-shaped gate electrode having a lateral portion on a top surface of the substrate and having a vertical portion at least partially inside a second cavity defined by opposing sidewalls of the vertically protruding portion of the substrate, wherein the lateral portion of the second T-shaped gate electrode is substantially parallel to the lateral portion of the first T-shaped gate electrode, and wherein the vertical portion of the second T-shaped gate electrode is substantially parallel to the vertical portion of the first T-shaped gate electrode.

10. A field effect transistor in a non-volatile EPROM, comprising:

a vertically extending gate electrode at least partially surrounded by a thin-body portion of a semiconductor substrate where a channel is to be formed.

11. A field effect transistor in a non-volatile EPROM, comprising:

a U-shaped thin-body portion of a semiconductor substrate where a channel is to be formed; and

a vertically extending gate electrode on opposing inner sidewalls of the U-shaped portion of the substrate.

12. A method of forming a field effect transistor on an active region of a semiconductor substrate, comprising:

forming a cavity in a vertically protruding thin-body portion of the substrate, wherein the cavity is defined by opposing sidewalls of the vertically protruding portion of the substrate; and

filling the cavity to form a vertically oriented gate electrode having at least a lower portion inside the cavity.

13. The method of claim 12, further comprising:

forming an insulating layer surrounding an upper portion of the vertically oriented gate electrode; and

forming a laterally oriented gate electrode on the insulating layer, wherein the laterally oriented gate electrode is connected to a top portion of the vertically oriented gate electrode.

14. The method of claim 13, wherein the vertically oriented gate electrode and the laterally oriented gate electrode are formed simultaneously.

15. The method of claim 12, wherein filling the cavity comprises:

filling the cavity in the vertically protruding portion of the substrate with polysilicon;

forming a heat-resistant metal layer on the surface of the substrate; and

applying a thermal treatment process to the substrate to form a vertically oriented gate electrode having at least a lower portion inside the cavity.

16. The method of claim 15, wherein filling the cavity further comprises controlling a thickness of the heat resistant metal layer and the duration of the thermal treatment process to form the vertically oriented gate electrode in the cavity.

17. The method of claim 12, further comprising forming spacers on the substrate before forming the cavity in the channel region to control a width of the channel region.

18. The method of claim 12, further comprising forming a lower insulating layer in the cavity between a bottom of the vertically oriented gate electrode and the substrate.

19. The method of claim 13, further comprising performing an ion implantation process after forming the insulating layer.

20. A method of forming a field effect transistor in a non-volatile EPROM, comprising:

forming a T-shaped gate electrode having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of the substrate.

21. A method for fabricating a semiconductor device, comprising:

forming an active region by etching an exposed semiconductor substrate using a mask pattern formed on a semiconductor substrate as an etch mask;

forming a shrunken mask pattern for exposing an edge of the active region by removing a portion of the mask pattern;

forming a device isolating layer to electrically insulate the active region by performing a planarization process until the shrunken mask pattern is exposed;

forming a dummy gate line by patterning the shrunken mask pattern and the device isolating layer until a top surface of the active region is exposed;

forming an insulating layer for filling a space between the dummy gate lines;

forming a second opening defined by the device isolating layer and the insulating layer by removing the patterned shrunken mask pattern of the dummy gate line;

forming a first opening by etching the active region exposed by the second opening;

forming a gate insulating layer in the first opening;

forming a gate line crossing over the device isolating layer and the insulating layer to fill the first opening and the second opening.

22. The method of claim 21, further comprising forming a lower insulating layer thicker than the gate insulating layer on a bottom of the first opening before forming the gate insulating layer.

23. The method of claim 22, wherein the forming of the lower insulating layer, comprises:

forming a silicon oxide layer on a bottom and a sidewall of the first opening by performing a thermal oxidation process;

forming a lower insulating material on the device isolating layer and the insulating layer to fill the first opening and the second opening;

removing a portion of the lower insulating material to fill the bottom of the first opening; and

removing the silicon oxide layer on the sidewall of the first opening,

wherein the gate insulating layer is formed on the exposed sidewall of the first opening.

24. The method of claim 23, wherein the lower insulating material comprises silicon nitride or non-doped silicon.

25. The method of claim 22, wherein forming the lower insulating layer comprises:

forming a silicon oxide layer on the device isolating layer and the insulating layer to fill the first opening and the second opening; and

removing a portion of the silicon oxide layer to fill a portion of the first opening.

26. The method of claim 21, wherein forming the gate line comprises:

forming a silicon layer to fill the first opening and the second opening;

forming a heat-resistant metal layer;

forming a metal silicide layer in the first opening and the second opening by performing a thermal treatment;

removing the non-reacted heat-resistant metal layer;

forming a conductive layer; and

patterning the conductive layer.

27. The method of claim 26, wherein the conductive layer comprises at least one of polysilicon, heat-resistant metal, or tungsten.

28. The method of claim 21, further comprising implanting channel ions after forming the insulating layer to fill the space between the dummy gate lines.

29. A method for fabricating a semiconductor device, comprising:

forming an active region by etching an exposed semiconductor substrate using a mask pattern formed on the semiconductor substrate as an etch mask;

forming a device isolating layer to electrically insulate the active region by performing a planarization process until the mask pattern is exposed after forming an insulating material;

forming a dummy gate line by patterning the mask pattern and the device isolating layer until a top surface of the active region is exposed;

forming an insulating layer to fill a space between the dummy gate lines;

forming a second opening defined by the device isolating layer and the insulating layer by removing the mask pattern component of the dummy gate line;

forming spacers on a sidewall of the second opening;

forming a first opening by etching the exposed active region exposed by the spacers;

forming a gate insulating layer in the first opening; and

forming a gate line crossing over the device isolating layer and the insulating layer with filling the first opening and the second opening.

30. The method as set forth in claim 29, further comprising forming a lower insulating layer thicker than the gate insulating layer on a bottom of the first opening before forming the gate insulating layer.

31. The method as set forth in claim 30, wherein forming the lower insulating layer comprises:

forming a silicon oxide layer on a bottom and a sidewall of the first opening by performing a thermal oxidation process;

forming a lower insulating material on the device isolating layer and the insulating layer to fill the first opening and the second opening;

removing a portion of the insulating material to fill a portion of the first opening; and

removing the silicon oxide layer on the sidewall of the first opening,

wherein the gate insulating layer is formed on the exposed sidewall of the first opening.

32. The method as set forth in claim 29, wherein the lower insulating material comprises silicon nitride or non-doped silicon.

33. The method as set forth in claim 30, wherein forming the lower insulating layer comprises:

forming a silicon oxide layer on the device isolating layer and the insulating layer to fill the first opening and the second opening; and

removing a portion of the silicon oxide layer to fill a portion of the first opening.