Semiconductor device and method of fabricating semiconductor device

• US 20050062146A1
• Filed: 09/22/2004
• Published: 03/24/2005
• Est. Priority Date: 09/24/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Noma, Takashi, Kaida, Takayuki, Shimizu, Ryu, Miwa, Tetsuya, Okigawa, Mitsuru
• Granted Patent: US 7,112,881 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A semiconductor device allowing simplification of a fabrication process is provided. This semiconductor device comprises a first insulator film, consisting of a single material, formed to be in contact with the upper surface of a semiconductor chip including a circuit, a first wire formed to be in contact with the upper surface of the first insulator film and a second wire formed to extend along the side surface and the lower surface of the semiconductor chip and connected to the lower surface of the first wire exposed by partially removing the first insulator film.

Claims

1. A semiconductor device comprising:

a first insulator film, consisting of a single material, formed to be in contact with the upper surface of a semiconductor chip including a circuit;

a first wire formed to be in contact with the upper surface of said first insulator film; and

a second wire formed to extend along the side surface and the lower surface of said semiconductor chip and connected to the lower surface of said first wire exposed by partially removing said first insulator film.

2. The semiconductor device according to claim 1, wherein

said first insulator film consists of a single SiO₂ film.

3. The semiconductor device according to claim 1, further comprising a second insulator film, formed on said first insulator film, consisting of a material different from that of said first insulator film and having a first opening, wherein

the lower surface of said first wire is in contact with the upper surface of said first insulator film and said second wire through said first opening of said second insulator film.

4. The semiconductor device according to claim 3, wherein

said second insulator film consists of an SiN film.

5. The semiconductor device according to claim 3, wherein

the width of said first wire is larger than the width of said first opening.

6. The semiconductor device according to claim 3, further comprising a third wire formed on said second insulator film, wherein

said second insulator film includes a second opening for connecting said third wire and said circuit of said semiconductor chip with each other.

7. The semiconductor device according to claim 6, wherein

said third wire consists of the same layer as said first wire.

8. The semiconductor device according to claim 1, further comprising a third insulator film, provided between said semiconductor chip and said second wire to isolate said semiconductor chip and said second wire from each other and formed to cover a prescribed region of the lower surface of said first insulator film, consisting of a material removable by etching means substantially identical to that for said first insulator film.

9. The semiconductor device according to claim 8, wherein

said etching means includes an etching solution employed for wet etching.

10. The semiconductor device according to claim 8, wherein

said third insulator film consists of the same material as said first insulator film.

11. A method of fabricating a semiconductor device, comprising steps of:

forming a first insulator film consisting of a single material to be in contact with the upper surface of a semiconductor chip including a circuit;

forming a first wire so that the lower surface thereof is in contact with the upper surface of said first insulator film;

exposing the lower surface of said first wire by at least partially etching said first insulator film from the lower surface side; and

connecting a second wire to the exposed lower surface of said first wire.

12. The method of fabricating a semiconductor device according to claim 11, wherein

said first insulator film consists of a single SiO₂ film.

13. The method of fabricating a semiconductor device according to claim 11, further comprising steps of:

forming a second insulator film consisting of a material different from that of said first insulator film on said first insulator film, and

forming a first opening in said second insulator film in advance of said step of forming said first wire so that the lower surface thereof is in contact with the upper surface of said first insulator film, wherein

said step of forming said first wire so that the lower surface thereof is in contact with the upper surface of said first insulator film includes a step of forming said first wire so that the lower surface thereof is in contact with the upper surface of said first insulator film through said first opening of said second insulator film.

14. The method of fabricating a semiconductor device according to claim 13, wherein

said second insulator film consists of an SiN film.

15. The method of fabricating a semiconductor device according to claim 13, wherein

the width of said first wire is larger than the width of said first opening.

16. The method of fabricating a semiconductor device according to claim 13, further comprising a step of forming a third wire on said second insulator film, wherein

said step of forming said first opening in said second insulator film includes a step of substantially simultaneously forming said first opening and a second opening for connecting said third wire and said circuit of said semiconductor chip with each other in said second insulator film by etching said second insulator film.

17. The method of fabricating a semiconductor device according to claim 16, wherein

said third wire consists of the same layer as said first wire.

18. The method of fabricating a semiconductor device according to claim 11, further comprising a step of forming a third insulator film consisting of a material removable by etching means substantially identical to that for said first insulator film to cover the lower surface of said first insulator film in advance of said step of exposing the lower surface of said first wire, wherein

said step of exposing the lower surface of said first wire includes a step of continuously partially etching said third insulator film and said first insulator film from the lower side by said identical etching means thereby exposing the lower surface of said first wire.

19. The method of fabricating a semiconductor device according to claim 18, wherein

said etching means includes an etching solution employed for wet etching.

20. The method of fabricating a semiconductor device according to claim 18, wherein

said third insulator film consists of the same material as said first insulator film.