Multiplexed pixel column architecture for imagers
First Claim
Patent Images
1. An imager device comprising:
- a plurality of pixels arranged in at least a first and second column, each column having a column line to which pixels in the column can be connected;
first and second sample and hold circuits for sampling and holding signals output from the pixels on said column lines; and
a multiplexer coupling at least first and second column lines with said first and second sample and hold circuits and being operable, in a first mode, to respectively couple said first and second sample and hold circuits to said first and second column lines and being operable, in a second mode, to respectively couple said first and second sample and hold circuits to said second and first column lines.
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Abstract
An imager with a multiplexer located at the pixel output line connected to associated column sample and hold circuitry. The multiplexer ensures that signals from pixels within a column are output to the correct output channels in the readout path. By having the multiplexer at the pixel output line, before any sample and hold circuitry, the imager can use simplified column select circuitry when signals are being read out to the output channels. As such, parasitic capacitance at the readout path is reduced, which produces faster readout speeds than typical imagers. In addition, the imager achieves lower readout noise and less power consumption than typical imagers.
35 Citations
68 Claims
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1. An imager device comprising:
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a plurality of pixels arranged in at least a first and second column, each column having a column line to which pixels in the column can be connected;
first and second sample and hold circuits for sampling and holding signals output from the pixels on said column lines; and
a multiplexer coupling at least first and second column lines with said first and second sample and hold circuits and being operable, in a first mode, to respectively couple said first and second sample and hold circuits to said first and second column lines and being operable, in a second mode, to respectively couple said first and second sample and hold circuits to said second and first column lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An image device comprising:
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a plurality of pixel signals arranged in N columns, each column having a respective column line to which the pixels in the column can be connected;
a plurality Y of sample and hold circuits for sampling and holding signals output from said pixels; and
a multiplexing circuit for coupling, in one operating mode, one of said N column lines to one of said sample and hold circuits and, in another operating mode, coupling a different one of said N columns to said one sample and hold circuit. - View Dependent Claims (15, 16)
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17. An imager device comprising:
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an array of pixels arranged in a plurality of rows and columns, each even numbered row having alternating green and red pixels, each odd numbered row having alternating blue and green pixels;
a plurality of first sample and hold circuits, each first sample and hold circuit being connected to a respective even numbered column of said array;
a plurality of second sample and hold circuits, each second sample and hold circuit being connected to a respective odd numbered column of said array; and
a plurality of switching circuits, each switching circuit being associated with and connected to a respective first sample and hold circuit and its associated even numbered column and a respective second sample and hold circuit and its associated odd numbered column, wherein said switching circuits being controlled such that signals associated with green pixels are sampled and held by said first sample and hold circuits and signals associated with the red and blue pixels are sampled and held by said second sample and hold circuits. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A processor system comprising:
an imager device comprising;
an array of pixels arranged in a plurality of rows and columns;
a plurality of first sample and hold circuits, each first sample and hold circuit being connected to a respective even numbered column of said array;
a plurality of second sample and hold circuits, each second sample and hold circuit being connected to a respective odd numbered column of said array; and
a multiplexer comprising a plurality of switching circuits, each switching circuit being associated with and connected to a respective first sample and hold circuit and its associated even numbered column and a respective second sample and hold circuit and its associated odd numbered column, wherein said switching circuits are controlled such that signals associated with a first pixel type are sampled and held by said first sample and hold circuits and signals of a pixel type different than the first pixel type are sampled and held by said second sample and hold circuits. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A processor system comprising:
an imager device, comprising;
an array of pixels arranged in a plurality of rows and columns, each even numbered row having alternating green and red pixels, each odd numbered row having alternating blue and green pixels;
a plurality of first sample and hold circuits, each first sample and hold circuit being connected to a respective even numbered column of said array;
a plurality of second sample and hold circuits, each second sample and hold circuit being connected to a respective odd numbered column of said array; and
a plurality of switching circuits, each switching circuit being associated with and connected to a respective first sample and hold circuit and its associated even numbered column and a respective second sample and hold circuit and its associated odd numbered column, wherein said switching circuits being controlled such that signals associated with green pixels are sampled and held by said first sample and hold circuits and signals associated with the red and blue pixels are sampled and held by said second sample and hold circuits. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
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57. A processor system comprising:
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an imager device, said imager device comprising;
a plurality of pixel signals arranged in N columns, each column having a respective column line to which the pixels in the column can be connected;
a plurality Y of sample and hold circuits for sampling and holding signals output from said pixels; and
a multiplexing circuit for coupling, in one operating mode, one of said N column lines to one of said sample and hold circuits and, in another operating mode, coupling a different one of said N columns to said one sample and hold circuit.
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58. A method of operating an imager device, said method comprising the steps of:
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storing signals associated with a first pixel type in a first storage device associated with a first column of pixels;
storing signals associated with a type other than the first pixel type in a second storage device associated with a second column of pixels;
outputting the signals from the first storage device to a first channel; and
outputting the signals from the second storage device to a second channel. - View Dependent Claims (59, 60, 61, 62)
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63. A method of operating a CMOS color imager device, said method comprising the steps of:
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storing signals associated with green pixels in a first storage device associated with a first column of pixels; and
storing signals associated with red and blue pixels in a second storage device associated with a second column of pixels. - View Dependent Claims (64, 65, 66, 67, 68)
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Specification