Hybrid circuit having nanotube electromechanical memory

• US 20050063210A1
• Filed: 10/13/2004
• Published: 03/24/2005
• Est. Priority Date: 07/25/2001
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Brock, Darren K., Segal, Brent M., Rueckes, Thomas
• Granted Patent: US 7,342,818 B2
• Time in Patent Office: Days
• US Class Current: 365/103
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: G11C 23/00 Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
• CPC Class Codes: Y10S 977/724 Devices having flexible or movable element
• CPC Class Codes: Y10S 977/734 Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/942 including protein logic element
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Claims

1. A hybrid memory circuit, comprising:

a substrate;

an electrically conductive trace disposed on the substrate;

a deflectable article having at least one nanotube disposed in spaced separation relative to the conductive trace, and wherein the position of the deflectable article represents a memory state of the memory circuit; and

an electronic selection circuit for selecting the deflectable article for operation in response to receiving a memory cell address.

2. A hybrid memory system, comprising:

an arrangement of memory cells, each memory cell having a nanotube element for storing cell states;

a cell selector circuit for receiving memory address information and for selecting at least one corresponding cell in response thereto, the cell selector circuit being constructed of transistors.