Memory cell and method for forming the same
First Claim
Patent Images
1. A plurality of memory cells formed on a surface of a substrate, comprising:
- an active region formed in the substrate;
a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and
a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.
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Accused Products
Abstract
A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.
20 Citations
100 Claims
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1. A plurality of memory cells formed on a surface of a substrate, comprising:
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an active region formed in the substrate;
a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and
a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory cell structure formed on a substrate having a surface, comprising:
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an active region formed in the substrate;
a semiconductor post formed on the active region;
first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
a memory cell capacitor formed on the semiconductor post; and
a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A memory device having an address bus and a data terminal, comprising:
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an array of memory cells formed on a substrate having a surface, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and
a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein a plurality of memory cells of the array of memory cells comprises;
an active region formed in the substrate;
a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and
a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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35. A memory device having an address bus and a data terminal, comprising:
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an array of memory cells formed on a substrate having a surface, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and
a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell of the array of memory cells comprises;
an active region formed in the substrate;
a semiconductor post formed on the active region;
first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
a memory cell capacitor formed on the semiconductor post; and
a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. A computer system, comprising:
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a processor having a processor bus;
an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and
a memory device coupled to the processor through the processor bus, the memory device comprising;
an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and
a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein a plurality of memory cells of the array of memory cells comprises;
an active region formed in the substrate;
a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and
a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59)
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60. A computer system, comprising:
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a processor having a processor bus;
an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and
a memory device coupled to the processor through the processor bus, the memory device comprising;
an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and
a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell of the array of memory cells comprises;
an active region formed in the substrate;
a semiconductor post formed on the active region;
first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
a memory cell capacitor formed on the semiconductor post; and
a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
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76. A method for forming a plurality of memory cells structures on a surface of a substrate, comprising:
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forming an active region in the substrate;
forming a plurality of posts on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
forming a plurality of contacts over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
forming a plurality of memory cell capacitors on a respective one of the plurality of posts; and
forming a plurality of gate structures adjacent a respective one of the plurality of posts to form a respective vertical transistor to electrically couple the respective memory cell capacitor to the active region. - View Dependent Claims (78, 79, 80, 81, 82, 83, 84)
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77. The method of 76 wherein forming the plurality of contacts comprises forming each contact of the plurality of contacts over a respective portion of the active region that extends laterally on the surface of the substrate from a respective region between a pair of posts.
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85. A method for forming a plurality of memory cells structures on a surface of a substrate, comprising:
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forming an active region in the substrate;
forming a semiconductor post on the active region;
forming first and second contacts on the active region and laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
forming a memory cell capacitor on the semiconductor post; and
forming a vertical access transistor having a gate adjacent the semiconductor post and to electrically couple the capacitor to the first and second contacts in response to being activated. - View Dependent Claims (86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100)
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Specification