Method for processing data packets received via a first interface and device for carrying out the method

• US 20050063405A1
• Filed: 09/13/2004
• Published: 03/24/2005
• Est. Priority Date: 09/19/2003
• Status: Active Grant

• Current Assignee: InterDigital Patent Holdings, Inc. (InterDigital, Inc.)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Gaedke, Klaus, Borsum, Malte
• Granted Patent: US 7,724,714 B2
• Time in Patent Office: Days
• US Class Current: 370/419
• CPC Class Codes: H04L 12/40052 High-speed IEEE 1394 serial bus bus transfer protocol on a daisy chain bus using an embedded synchronisation G06F13/426
• CPC Class Codes: H04L 12/40071 Packet processing; Packet format adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04W 28/14 using intermediate storage
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]

Abstract

During the transmission of data packets received on a wired connection via a first interface (e.g. IEEE 1394 interface) via a second interface designed for the wireless transmission of data, e.g. HIPERLAN/2 interface, the problem exists that between receiving the data and transmitting the data via the second interface a relatively large delay time can arise which must be bridged by means of a suitably dimensioned buffer memory. The invention provides means that enable the maximum delay time to be further reduced. For this purpose, according to the invention, the necessary processing of the received IEEE 1394 bus packets is already performed section by section immediately after a received data packet has arrived. After the complete number of bus packets falling within a transmission frame has been received, there is therefore no longer any lengthy processing time required and the probability of missing the time slots reserved in the next transmission frame is significantly reduced. The buffer memory for bridging the delay time period can therefore be correspondingly smaller.

Claims

1. Method for processing data packets received via a first interface for outputting via a second interface, in which a specific time-slot pattern is observed for outputting the data via the second interface, wherein a specific number of received data packets falls within the time-slot pattern for the output of the data, wherein the reformatting of the data is performed section by section, in each case after receiving one of the data packets.

2. Method according to claim 1, wherein the output of the data via the second interface takes place in reserved time slots in accordance with the TDMA method, where TDMA stands for Time Division Multiplex Access.

3. Method according to claim 2, wherein, in the case where a reserved time slot in a transmission frame has been missed, the still available reserved time slots of said transmission frame are filled up with the reformatted data that is already available.

4. Method according to claim 1, wherein a time-slot pattern that has been advanced by a given amount is used for internal processing of the received data packets instead of the output time-slot pattern.

5. Method according to claim 1, wherein a re-segmenting is performed for reformatting the received data.

6. Method according to claim 1, wherein the first interface corresponds to an IEEE 1394 interface and the second interface corresponds to a HIPERLAN interface for wireless transmission of data.

7. Device for carrying out the method according to claim 1, having a first interface for receiving data packets, having a second interface for outputting the data packets, in which a specific time-slot pattern must be observed for outputting the data via the second interface, and a specific number of received data packets falls within the time-slot pattern for the output of the data, wherein the device contains reformatting means which perform a reformatting of the data section by section, in each case after receiving one of the data packets.

8. Device according to claim 7, wherein the second interface for transmitting the data in reserved time slots is designed in accordance with the TDMA method, where TDMA stands for Time Division Multiplex Access.

9. Device according to claim 8, wherein filling means are provided for the case where a reserved time slot in a transmission frame has been missed, which means fill up the still available reserved time slots of said transmission frame with the reformatted data that is already available.

10. Device according to claim 7, wherein time-slot pattern adjustment means are provided which advance the output time-slot pattern for the internal, section-by-section reformatting of the data by a given amount.

11. Device according to claim 7, wherein the reformatting means have a processing step for resegmenting the received data.

12. Device according to claim 7, wherein the first interface corresponds to an IEEE 1394 interface and the second interface corresponds to a HIPERLAN interface for wireless transmission of data.