Method for the improved recognition of the validity of IEEE 802.11a signals, and circuit arrangement for performing the method

• US 20050063495A1
• Filed: 08/24/2004
• Published: 03/24/2005
• Est. Priority Date: 08/29/2003
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Aue, Volker
• Granted Patent: US 7,447,281 B2
• Time in Patent Office: Days
• US Class Current: 375/341
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 27/2602 Signal structure

Abstract

To improve the recognition of the validity of coded control information that is transmitted, together with associated useful data, as a data signal and that is decoded at the receiver by means of a Viterbi decoder (VDCOD), it is proposed that at least an end section of the received, convolution-coded control information is prefixed to this same information, the length of the end section being at least that of the convolution-coded tail bit-sequence, and the information that has been assembled in this way being fed to the Viterbi decoder to allow the convolution-coded control information to be decoded.

Claims

1. A method for recognizing the validity of convolution-coded control information that is transmitted, together with useful data that is associated with and follows it, as a data signal over a transmission path subject to interference, the control information having, at its end, a preset, (k-1) long tail bit-sequence and the convolutional encoder, which has a constraint length of k, being preloaded with the tail bit-sequence prior to the convolutional coding of the control information, and, after transmission, the received, convolution-coded control information being decoded in a Viterbi decoder on the basis of finding a path in the trellis diagram having a maximum or minimum accumulated metric, characterized in that at least an end section of the received, convolution-coded control information is prefixed to this same information, the length of the end section being at least that of the convolution-coded tail bit-sequence, and the information that has been assembled in this way being fed to the Viterbi decoder (VDCOD) to allow the convolution-coded control information to be decoded.

2. A method as claimed in claim 1, characterized in that the received, convolution-coded control information is prefixed to this same information, the two identical sets of convolution-coded control information, which are arranged one behind the other, being fed to the Viterbi decoder (VDCOD).

3. A method as claimed in claim 2, characterized in that sections of control information that are associated in the given case in the two sets of control information are selected from the decoded bit-sequence and are compared with one another, the result of the comparison of the two sections being used as a partial criterion of the validity of the received control information, or the received control information being accepted as valid in response to a match between the two sections.

4. A method as claimed in claim 3, characterized in that the sections of control information that are selected each comprise the complete set of control information not including the associated tail bit-sequence.

5. A method as claimed in claim 1, characterized in that, in the decoded bit-sequence, that section of the bit-sequence that lies between the two decoded sections of useful control information data is compared with the tail bit-sequence, the result of the comparison of the two sections being used as a partial criterion of the validity of the received control information, or the received control information being accepted as valid in response to a match between the two sections.

6. A method as claimed in claim 4, characterized in that a signal is generated in each case in response to the checks, and the signals from two checks are gated with one another logically to provide a signal associated with the validity of the control information.

7. A method as claimed in claim 1, characterized in that the received, convolution-coded control information is prefixed with precisely the received, convolution-coded tail bit-sequence, and the decoded bit-sequence that corresponds to the convolution-coded bit-sequence that is added as a prefix is compared with the tail bit-sequence, the result of the comparison being used as a partial criterion of the validity of the received control information, or the received control information being accepted as valid in response to a match.

8. A method as claimed in claim 1, characterized in that the state that acts as a starting state for the first bit of the control information on the state path determined in the trellis diagram is compared with a preset state laid down by the tail bit-sequence, the result of the comparison being used as a partial criterion of the validity of the received control information, or the received control information being accepted as valid in response to a match.

9. A method as claimed in claim 1, characterized in that the data signal is formatted to the IEEE 802.11a standard, the control information being the 24-bit-wide PLCP (physical layer convergence procedure) header.

10. A method as claimed in claim 1, characterized in that an item of parity information contained in the control information and/or plausibility appraisals relating to at least one subfield of the control information such as LENGTH and/or RATE are used to enable the validity of the recovered control information to be recognized.

11. A method as claimed in claim 1, characterized in that, in an IEEE 802.11g network, on the control information being recognized as invalid, the possibility of an OFDM (orthogonal frequency division multiplexing) modulated signal is ruled out and a check is made to see whether the signal present is some other standardized modulated signal and in particular a DSSS (direct sequence spread spectrum) or a CCK (complementary code keying) modulated signal.

12. A method as claimed in claim 1, characterized in that the convolution-coded control information is acquired as a soft bit-sequence, and the assembled information is generated prior to passage through a deinterleaver (DVS) inserted upstream of the Viterbi decoder VDCOD), the soft bit-sequence that represents the control information being read into a buffer store.

13. A circuit arrangement for recognizing the validity of convolution-coded control information (SIGNAL) that is transmitted, together with useful data that is associated with and follows it, as a data signal over a transmission path subject to interference, the control information having a preset tail bit-sequence, said circuit arrangement comprising a Viterbi decoder in which the received, convolution-coded control information is able to be decoded on the basis of finding a path in the trellis diagram having a maximum or minimum accumulated metric, particularly for performing a method as claimed in claim 1, characterized by a means (Buffer, Select) inserted upstream of the Viterbi decoder (VDCOD), for generating an assembled signal in which at least an end section of the received, convolution-coded control information is arranged in front of this same control information, the length of this section being at least that of the convolution-coded tail bit-sequence, and by a means for feeding the assembled information to the Viterbi decoder.

14. A circuit arrangement as claimed in claim 13, characterized by a means (S, CompareZeros, CompareEqual, &

) inserted downstream of the Viterbi decoder for selecting and comparing associated sections of control information in the assembled bit-sequence that is decoded, and for forming a logic value that specifies a match between the sections of control information.

15. A circuit arrangement as claimed in claim 14, characterized by a means (S, CompareZeros) inserted downstream of the Viterbi decoder for selecting that bit-sequence section that is associated with a tail bit-sequence and that is situated between the associated sections of control information in the bit-sequence that is decoded and for comparing the bit-sequence section in question with the tail bit-sequence, and for forming a logic value that states that the comparison has found a match.

16. A circuit arrangement as claimed in claim 14, characterized by a logic gating means (&

) that generates a signal specifying that the control information is valid in response to the two logic values.

17. A circuit arrangement as claimed in any one of claims 13 to 16, characterized by a means associated with the Viterbi decoder for comparing a state at a predetermined transition in the trellis diagram on the most probable state path that is determined, with a preset state that depends on the tail bit-sequence.