Method of fabricating a semiconductor component with active regions separated by isolation trenches

• US 20050064678A1
• Filed: 09/20/2004
• Published: 03/24/2005
• Est. Priority Date: 09/19/2003
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Graf, Michael, Dudek, Volker
• Granted Patent: US 7,078,324 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

To form a semiconductor component having active regions separated from one another by trenches as isolation structures, a method involves forming a shallow trench in a semiconductor body, thereafter forming a deep trench within the shallow trench in the semiconductor body, and thereafter completely driving dopant atoms into the semiconductor body to form a well region doped with the dopant. The dopant may be previously introduced by implantation into a surface layer, and then the dopant is finally completely driven into the well region by thermally supported diffusion after forming the deep trench. The shallow and deep trenches together form a compound trench with stepped side walls. Two oppositely doped wells may be formed on opposite sides of the compound trench, which thus isolates the two wells from one another. Active regions may be formed in the two wells.

Claims

1. A method of fabricating a semiconductor component, comprising steps:

a) forming at least one shallow trench in a semiconductor body;

b) after said step a), forming at least one deep trench within said at least one shallow trench in said semiconductor body;

c) providing at least one dopant; and

d) at the earliest after said step b), driving said at least one dopant into said semiconductor body to form at least one well respectively doped with said at least one dopant in said semiconductor body.

2. The method according to claim 1, further comprising forming first and second active regions in said semiconductor body such that said first and second active regions are separated from one another by said shallow trench and said deep trench.

3. The method according to claim 1, wherein said step a) comprises forming a plurality of said shallow trenches, and said step b) comprises forming a plurality of said deep trenches respectively within said shallow trenches.

4. The method according to claim 1, wherein said steps a) and b) are carried out to form said deep trench deeper and narrower than said shallow trench.

5. The method according to claim 4, wherein said steps a) and b) are carried out so that said shallow trench and said deep trench together form a compound trench having a relatively shallower and wider portion and a relatively deeper and narrower portion, and having stepped sidewalls with a shoulder at a transition between said relatively shallower and wider portion and said relatively deeper and narrower portion.

6. The method according to claim 5, wherein said stepped sidewalls slope so that said shallow trench and said deep trench taper.

7. The method according to claim 1, wherein said step c) comprises providing first and second different ones of said dopants having opposite conductivity types, and said step d) comprises forming first and second ones of said wells that are respectively doped with said first and second dopants having opposite conductivity types and that are respectively located on opposite sides of said shallow trench and said deep trench.

8. The method according to claim 1, further comprising locating and controlling said forming of said shallow trench and/or said deep trench, and/or said driving of said at least one dopant to form said at least one well, so that said well is at least partially bounded by said shallow trench and/or said deep trench.

9. The method according to claim 1, wherein said step d) involves the complete driving of said at least one dopant into said semiconductor body to form said at least one well, without any dopant drive taking place before said step d).

10. The method according to claim 1, wherein said steps b) and d) are carried out so that said deep trench has a depth at least as great as a depth of said well.

11. The method according to claim 1, wherein said semiconductor body comprises a silicon layer on an insulating layer, said step b) comprises forming said deep trench in said silicon layer to a trench depth reaching said insulating layer, and said step d) comprises forming said well in said silicon layer to a well depth reaching said insulating layer.

12. The method according to claim 1, wherein said step a) comprises carrying out an STI process to form said at least one shallow trench.

13. The method according to claim 1, wherein said step a) comprises providing on said semiconductor body a first mask with a first opening and etching said semiconductor body through said first opening to form said at least one shallow trench, and wherein said step b) comprises providing on said first mask a second mask with a second opening in registration with said first opening of said first mask and etching said semiconductor body through said second opening to form said at least one deep trench.

14. The method according to claim 13, wherein said second mask fills said shallow trench within said first opening except for said second opening so as to prevent further etching of said shallow trench during said step b).

15. The method according to claim 13, further comprising removing said first mask and said second mask before said step d).

16. The method according to claim 1, further comprising providing an insulating material in common in said shallow trench and said deep trench.

17. The method according to claim 1, further comprising providing a liner oxide layer on inner surfaces of said shallow trench and said deep trench.

18. The method according to claim 17, comprising providing said liner oxide layer before said step d).

19. The method according to claim 17, further comprising filling said shallow trench and said deep trench with an oxide or polysilicon after providing said liner oxide layer.

20. The method according to claim 1, further comprising filling said shallow trench and said deep trench with an oxide or polysilicon.

21. The method according to claim 1, wherein said step c) comprises at least one ion implantation of said at least one dopant into said semiconductor body, and said step d) comprises a thermally supported diffusion, at an elevated temperature, of said at least one dopant completely into said semiconductor body to form said at least one well.

22. The method according to claim 21, wherein said step c) is carried out before said step a).

23. The method according to claim 21, wherein said step c) comprises implanting said at least one dopant into at least one surface layer of said semiconductor body, and said step d) comprises said thermally supported diffusion of said at least one dopant from said at least one surface layer into an entire volume of said at least one well in said semiconductor body.

24. A method of fabricating a semiconductor component, comprising, in sequence, steps:

a) applying at least one mask leaving first and second open areas on a semiconductor body;

b) implanting first and second dopants of opposite polarity respectively through said first and second open areas respectively into first and second surface regions of said semiconductor body;

c) forming a shallow trench in said semiconductor body between and/or in said first and second surface regions;

d) forming a deep trench within said shallow trench in said semiconductor body;

e) forming a thin oxide layer on surfaces of said shallow trench and said deep trench;

f) by a thermally supported diffusion process, driving said first and second dopants from said first and second surface regions deeper into said semiconductor body to respectively define first and second wells respectively doped with said first and second dopants on opposite sides of said shallow trench and said deep trench in said semiconductor body; and

g) filling said shallow trench and said deep trench with an insulating material.

25. The method according to claim 24, wherein said first and second surface regions border directly on one another in said step b), and forming said shallow trench in said step c) removes a respective portion of each of said first and second surface regions.