Trench capacitor DRAM cell using buried oxide as array top oxide

• US 20050064710A1
• Filed: 07/06/2004
• Published: 03/24/2005
• Est. Priority Date: 06/18/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Deok-Kee Kim, Dureseti Chidambarrao, Ramachandra Divakaruni
• Inventors: Kim, Deok-kee, Divakaruni, Ramachandra, Chidambarrao, Dureseti
• Granted Patent: US 7,195,972 B2
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.

Claims

1. A method of forming an integrated circuit containing a DRAM array in an SOI wafer comprising the steps of:

preparing an SOI substrate having a device layer of silicon separated from a bulk substrate by a BOX layer, said device layer comprising an array area and a support area outside the array area;

etching an array of deep trenches in the array area and forming capacitors therein;

forming vertical transistors below the BOX;

forming gate stack/wordlines in the array and gate stacks in the support area;

using the gate stack in the array as a mask, etching the device layer in the array;

etching the BOX in the array using a block mask, thereby forming passing wordlines insulated from the substrate by the BOX; and

completing the circuit.

2. A method according to claim 1, in which the step of patterning gate stacks in the array and in the support comprises the steps of:

depositing a first layer of poly;

removing the first layer of poly in the array area and patterning the first layer of poly with a gate pattern outside the array;

depositing a second layer of poly;

patterning the first and the second layer of poly with a gate pattern outside the array and the second layer of poly and the SOI layer with a first level interconnect pattern in the array.

3. A method according to claim 2, in which the first and second layers of poly have a combined thickness adapted to form a MOSFET gate.

4. A method according to claim 2, in which the second layer of poly and the device layer have a combined thickness adapted to form a wordline.

5. A method according to claim 3, in which the second layer of poly and the device layer have a combined thickness adapted to form a wordline.

6. A method according to claim 1, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

7. A method according to claim 2, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

8. A method according to claim 3, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

9. A method according to claim 4, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

10. A method according to claim 2, in which the first and the second layers of poly in the supports are patterned in the same etching step.

11. A method according to claim 2, in which the second layer of poly and the device layer in the array are patterned in the same etching step.

30. A method according to claim 3, in which the second layer of poly and the device layer in the array are patterned in the same etching step.

12. An integrated circuit comprising a DRAM array in an SOI wafer comprising:

an SOI substrate having a device layer of silicon separated from a bulk substrate by a BOX layer, said device layer comprising an array area and a logic area outside the array area;

a set of deep trenches in the array area having capacitors formed therein;

a set of vertical transistors in the array disposed below the BOX; and

a set of gate/wordline structures in the array arranged with wordlines insulated from the substrate by a dielectric.

13. An integrated circuit according to claim 12, in which the vertical transistors have upper electrodes formed below the BOX and connected through apertures formed in the BOX to interconnect members.

14. An integrated circuit according to claim 12, in which portions of the BOX in the array remain below wordline structures, thereby isolating the wordline structures from the substrate.

15. An integrated circuit according to claim 13, in which portions of the BOX in the array remain below wordline structures, thereby isolating the wordline structures from the substrate.

16. An integrated circuit according to claim 12, in which the array is connected with passing wordlines, whereby alternate wordlines make contact to the gates of vertical transistors and pass over upper electrodes formed below the BOX and connected through apertures formed in the BOX to interconnect members that extend vertically between adjacent wordlines.

17. An integrated circuit according to claim 16, in which portions of the BOX in the array remain below wordline structures, thereby isolating the wordline structures from the substrate.

18. An integrated circuit according to claim 12, in which a set of logic gates are formed from a second layer of poly deposited on a first layer of poly and having a combined poly thickness.

19. An integrated circuit according to claim 18, in which a set of cell gate contacts are formed from the second layer of poly deposited on gate electrode and having a gate contact poly thickness less than the combined thickness.

20. A method of forming an integrated circuit containing a DRAM array in an SOI wafer comprising the steps of:

preparing an SOI substrate having a device layer of silicon separated from a bulk substrate by a BOX layer, said device layer comprising an array area and a support area outside said array area;

etching an array of deep trenches in said array area and forming capacitors therein;

forming a set of vertical pass transistors in said array of deep trenches, said vertical pass transistors being located below said BOX and having gates in said array of deep trenches;

depositing a layer of conductive gate material in said array and in said support area;

patterning said layer of conductive gate material to form gate stack/wordlines in said array and gate stacks in said support area;

using the gate stack in the array as a mask, etching said device layer in said array thereby exposing BOX areas;

etching said BOX areas in said array using a block mask outside said array, thereby forming passing wordlines insulated from the substrate by the BOX; and

completing the circuit.

21. A method according to claim 20, in which the step of patterning gate stacks in the array and in the support comprises the steps of:

depositing a first layer of poly;

removing the first layer of poly in the array area and patterning the first layer of poly with a gate pattern outside the array;

depositing a second layer of poly;

patterning the first and the second layer of poly with a gate pattern outside the array and the second layer of poly and the SOI layer with a first level interconnect pattern in the array.

22. A method according to claim 21, in which the first and second layers of poly have a combined thickness adapted to form a MOSFET gate.

23. A method according to claim 21, in which the second layer of poly and the device layer have a combined thickness adapted to form a wordline.

24. A method according to claim 22, in which the second layer of poly and the device layer have a combined thickness adapted to form a wordline.

25. A method according to claim 20, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

26. A method according to claim 21, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

27. A method according to claim 22, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

28. A method according to claim 23, in which the step of etching the BOX opens a set of apertures exposing upper electrodes of the vertical transistors.

29. A method according to claim 21, in which the first and the second layers of poly in the supports are patterned in the same etching step.