Implantable medical device configured for diagnostic emulation through serial communication

• US 20050066088A1
• Filed: 09/30/2004
• Published: 03/24/2005
• Est. Priority Date: 06/16/2000
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc), Medtronic Vascular (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Jensen, Steve, Helfinstine, Alan R.
• Granted Patent: US 7,289,852 B2
• Time in Patent Office: Days
• US Class Current: 710/71
• CPC Class Codes: A61M 2205/3523 using telemetric means
• CPC Class Codes: A61M 5/14276 specially adapted for implantation
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/3605 Implantable neurostimulators for stimulating central or peripheral nerve system
• CPC Class Codes: A61N 1/37 Monitoring; Protecting
• CPC Class Codes: A61N 1/37241 providing test stimulations
• CPC Class Codes: A61N 1/37252 Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
• CPC Class Codes: A61N 1/37254 Pacemaker or defibrillator security, e.g. to prevent or inhibit programming alterations by hackers or unauthorised individuals

Abstract

An implantable medical device (IMD) with internal processor is configured for diagnostic emulation using an external processor coupled to the internal processor through a high speed serial link. The native external processor parallel data and address bus content can be converted to a serial communications stream, sent into the device, converted back to parallel address and data bus formats, and used to drive the device in place of the internal processor. The serial communication allows use of a small number of contact pads, conductors, or feed-throughs, depending on the device. Some devices allow serialized communication through the feed-through typically used for electrical stimulation. The devices can be used to enhance diagnostic testing with capabilities such as faster testing and more realistic testing. The IMD can be a wide variety of implantable devices such as neuro stimulators, pace makers, defibrillators, drug delivery pumps, diagnostic recorders, cochlear implants, and the like. The device can have a bus switch, which when activated, decouples the internal processor, and couples address and data buses containing information and commands provided by the external emulator through the serial communication channel.

Claims

1. A medical device (MD) configured for diagnostic emulation including being configured for coupling to an external processor, the MD comprising:

an internal processor;

an internal clock coupled to the internal processor;

memory;

a bus switch coupled to the internal processor and to the memory to read and write the memory;

wherein

a first address bus couples the internal processor to the bus switch, wherein

a first data bus couples the internal processor to the bus switch;

a second address bus coupled to the bus switch;

a second data bus coupled to the bus switch;

wherein the bus switch is adapted to receive an activation signal, wherein upon receiving the activation signal the bus switch is configured to couple the second address bus to the memory, couple the second data bus to the memory, and decouple the internal processor from the memory; and

a serial-parallel interface having a serial communications port, and a parallel port coupled to the second address bus and the second data bus, wherein the serial-parallel interface is configured to receive a serial format address through the serial communications port and output a parallel format address to the second address bus through the parallel port.

2. The MD of claim 1, further comprising at least one interrupt line coupled to the serial-parallel interface, in which the serial-parallel interface is configured to output data from the interrupt line in serial format through the serial communication port.

3. The MD of claim 1, in which the serial port includes at least one output line and one input line.

4. The MD of claim 1, in which the serial port includes at least one output line and two input lines.

5. The MD of claim 1, further comprising a plurality of electrically conductive lines coupled to the serial-parallel interface serial communication port and to a feedthrough connector.

6. The MD of claim 1, further comprising:

an electrical stimulator having stimulator output lines;

a feedthrough connector including a plurality of connections for electrically coupling to an external electrical device;

a switch coupled to the stimulator output lines and to the serial-parallel interface serial communication port and to the feedthrough connector, wherein the switch is configured to establish electrical continuity between the feedthrough connector and either the serial-parallel interface serial communication port or the stimulator output lines, but not both at the same time, such that the serial-parallel interface serial communication port can be communicated with through the feedthrough connector.

7. The MD of claim 1 wherein the MD is substantially a production MD.

8. The MD of claim 1 wherein the bus switch when activated decouples the internal processor from the first address bus and the first data bus by switching an internal processor address output to substantially zero and switching an internal processor data bus output to high impedance.

9. The MD of claim 1 wherein the internal processor has a reset condition, wherein the bus switch when activated holds the internal processor in the reset condition.

10. The MD of claim 1 wherein the bus switch comprises an address bus switch and a data bus switch, wherein the address bus switch is coupled to the first and second address buses and the data bus switch is coupled to the first and second data bus.

11. The MD of claim 10, further comprising a memory management unit wherein the address bus switch is part of the memory management unit.

12. The MD of claim 10 wherein the data bus switch comprises tri-state logic gates.

13. The MD of claim 1, wherein the MD is adapted to be coupled to an external clock, the MD further comprising:

clock sync logic;

an external clock connector for coupling to the external clock; and

a clock line coupling the clock sync logic to the internal clock and the external clock connector.

14. The MD of claim 13 wherein the MD includes internal logic, wherein the external and internal clocks operate at different speeds, and wherein the clock sync logic synchronizes the MD internal logic with the external clock.

15. The MD of claim 1, further comprising a functional module coupled to the bus switch.

16. The MD of claim 15 wherein the functional module performs a function selected from the group of functions consisting of:

therapy, therapy measurement, power management, recharge, and telemetry.

17. The MD of claim 1 wherein the MD is selected from the group consisting of:

a neuro stimulator, a pacemaker, a defibrillator, a drug delivery pump, a diagnostic recorder, and a cochlear implant.

18. The MD of claim 1, in which the MD is configured to be hermetically sealed and implanted in a human body

19. The MD of claim 18, in which the MD includes a hermetically sealable housing,

20. The MD of claim 18, in which the MD is hermetically sealed within a housing,

21. The MD of claim 1, in which the internal processor is selected from the group consisting of microprocessors, ASIC state machines, and logic gate arrays.

22. A medical device (MD) configured for diagnostic emulation including being configured for coupling to an external processor, the MD comprising:

an internal processor;

an internal clock coupled to the internal processor;

memory coupled to the internal processor in a parallel format connection;

wherein

a first address bus couples the internal processor to the memory;

wherein

a first address a second address bus;

a second data bus;

means for receiving an externally generated activation signal;

means for bus switching to selectively switch the memory from operation by the internal processor through the first address and first data bus to configuration for operation by the external processor through the second address bus and second data bus, responsive to reception of the externally generated activation signal;

means for sending and receiving serial data communication to and from the MD;

means for converting serial format data into parallel format;

coupled to the second address bus and second data bus; and

means for converting the memory parallel data to serial format coupled to the second address bus and second data bus.

23. The MD of claim 22, wherein the MD includes interrupt data, wherein the means for converting parallel format data to serial format data is configured to convert the interrupt data into serial format.

24. The MD of claim 22, further comprising:

means for housing contents of the MD;

means for electrically stimulating a patient;

means for connecting to an external an electrical signal;

means for switching the electrically stimulating means and the serial-parallel interface means through to the external connecting means, wherein the switching means is configured to put the external connecting means in electrical communication with either the stimulating means or the serial-parallel interface means but not both at the same time, such that the means for serial-parallel interface can be communicated with from outside of the housing.

25. The MD of claim 22, wherein the MD includes internal logic, wherein the internal clock and the external clock operate at different speeds, further comprising means for clock synchronization to synchronize the MD internal logic with the external clock.

26. The MD of claim 22, in which the internal processor is selected from the group consisting of microprocessors, ASIC state machines, and logic gate arrays.

27. The MD of claim 22 further comprising a hermetically sealed housing and a feedthrough providing electrical connectivity extending through the housing external connecting means.

28. A method for externally controlling an implantable medical device (IMD) having an internal processor, the method comprising:

sending an activation signal to the IMD, thereby causing the IMD to decouple an internal processor and to be in a mode for allowing an external device to read and write data to memory in the IMD at a sustained speed substantially as fast as the internal processor;

sending a first serial communication stream to the IMD including an address to be read

reading data from the address in the IMD;

sending the data out in a second serial communication stream; and

receiving the second serial communication stream external to the IMD.

29. The method of claim 28, further comprising sending a third serial communication stream to the IMD including an address to be read and data to be written into the IMD at the address and receiving a fourth serial communications stream from the IMD including data read from the address in the third serial communications stream.

30. The method of claim 28, further comprising converting the first serial communication stream to a parallel format within the IMD.

31. An implantable medical device (LMD) comprising:

an internal processor;

a memory coupled to the internal processor;

an interface device configured to access the memory, in which the interface device is configured to receive a first serial format signal containing a first address, access the memory at the first address, and output a second serial format signal containing the memory contents at the first address, in which the interface device is also configured to receive a third serial format signal containing a memory address and a fourth serial format signal containing data to be written to the memory, and to write the data received in the fourth serial format signal to the memory at the third serial format signal address;

in which the IMD is configured to decouple the internal processor from the memory and to allow an external device to read and write the memory at substantially the same speed as the internal processor, through serial signals sent to and from the interface device.

32. The IMD of claim 31, in which the IMD interface device includes a bus switch, in which the processor is coupled to the memory through the bus switch, in which the interface device includes a serial-parallel converter including a serial format interface port and a parallel format interface port, in which the parallel format interface port is coupled to the bus switch, such that either the processor or the serial-parallel converter can control the memory through the bus switch.

33. The IMD of claim 32, further comprising an electrical stimulator disposed within the IMD, including a stimulator output portion, further comprising a switch coupled to the serial-parallel converter serial format interface port, to the stimulator output portion, and to an externally accessible connector, in which the switch allows either the serial-parallel converter or the stimulator output portion to be externally electrically accessible, but not both at the same time.

34. The IMD of claim 31, further comprising a clock synch line that transmits timing information about the internal clock to a location outside of the IMD.

35. A method for externally controlling an implantable medical device (IMD), the method comprising:

sending a signal to decouple to an internal processor in the IMD from a memory bus and a data bus in the IMD;

sending a first serial data stream to the IMD containing a memory address to read; and

receiving a second serial data stream from the IMD containing data from the memory location at the address in the first serial signal.

36. The method of claim 35, further comprising sending a third serial data stream to the IMD containing a memory address and sending a fourth serial data stream containing data to be written to the address in the third data stream.

37. The method of claim 36, further comprising receiving a clock synch signal from the IMD containing clock timing information about a clock in the MD and synchronizing an external device to the internal clock at least in part based on the received clock synch signal.

38. The method of claim 37, further comprising decoupling an electrical stimulator from an externally accessible connector, and coupling an internal serial connector link to the externally accessible connector, in which the sending and receiving serial data occurs through the externally accessible connector.