Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications

• US 20050066262A1
• Filed: 08/31/2004
• Published: 03/24/2005
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: DTVG Licensing, Inc. (AT&T, Inc.)
• Original Assignee: The DIRECTV Group, Inc. (AT&T, Inc.)
• Inventors: Sun, Feng-Wen, Lee, Lin-Nan, Eroz, Mustafa
• Granted Patent: US 7,237,174 B2
• Time in Patent Office: Days
• US Class Current: 714/800
• CPC Class Codes: H03M 13/1134 Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/118 Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure H03M13/1165 takes precedence
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence

Abstract

An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Claims

1. A method for supporting transmission of a Low Density Parity Check (LDPC) coded signal, comprising:

receiving information bits; and

generating, based on the information bits, an Low Density Parity Check (LDPC) code according to one of Tables 1-10 for transmission as the LDPC coded signal, each of the Tables 1-10 specifying address of parity bit accumulators;

TABLE 1Address of Parity Bit Accumulators (Shortened from Rate 1/2)20 712 2386 6354 4061 1062 5045 515821 2543 5748 4822 2348 3089 6328 587622 926 5701 269 3693 2438 3190 350723 2802 4520 3577 5324 1091 4667 444924 5140 2003 1263 4742 6497 1185 62020 4046 69341 2855 662 6694 2123 3439 11584 3850 44225 5924 2906 1467 40497 7820 22428 4606 30809 4633 787710 3884 686811 8935 499612 3028 76413 5988 105714 7411 3450

TABLE 2Address of Parity Bit Accumulators (Rate 3/5)2765 5713 6426 3596 1374 4811 2182 544 3394 2840 4310 7714951 211 2208 723 1246 2928 398 5739 265 5601 5993 2615210 4730 5777 3096 4282 6238 4939 1119 6463 5298 6320 40164167 2063 4757 3157 5664 3956 6045 563 4284 2441 3412 63344201 2428 4474 59 1721 736 2997 428 3807 1513 4732 61952670 3081 5139 3736 1999 5889 4362 3806 4534 5409 6384 58095516 1622 2906 3285 1257 5797 3816 817 875 2311 3543 12054244 2184 5415 1705 5642 4886 2333 287 1848 1121 3595 60222142 2830 4069 5654 1295 2951 3919 1356 884 1786 396 47380 2161 26531 1380 14612 2502 37073 3971 10574 5985 60625 1733 60286 3786 19367 4292 9568 5692 34179 266 487810 4913 324711 4763 393712 3590 290313 2566 421514 5208 470715 3940 338816 5109 455617 4908 4177

TABLE 3Address of Parity Bit Accumulators (Rate 2/3)0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 26221 122 1516 3448 2880 1407 1847 3799 3529 373 971 4358 31082 259 3399 929 2650 864 3996 3833 107 5287 164 3125 23503 342 35294 4198 21475 1880 48366 3864 49107 243 15428 3011 14369 2167 251210 4606 100311 2835 70512 3426 236513 3848 247414 1360 17430 163 25361 2583 11802 1542 5093 4418 10054 5212 51175 2155 29226 347 26967 226 42968 1560 4879 3926 164010 149 292811 2364 56312 635 68813 231 168414 1129 3894

TABLE 4Address of Parity Bit Accumulators (Shortened from Rate 3/4)3 3198 478 4207 1481 1009 2616 1924 3437 554 683 18014 2681 21355 3107 40276 2637 33737 3830 34498 4129 20609 4184 274210 3946 107011 2239 9840 1458 30311 3003 13282 1137 17163 132 37254 1817 6385 1774 34476 3632 12577 542 36948 1015 19459 1948 41210 995 223811 4141 19070 2480 30791 3021 10882 713 13793 997 39034 2323 33615 1110 9866 2532 1427 1690 24058 1298 18819 615 17410 1648 311211 1415 2808

TABLE 5Address of Parity Bit Accumulators (Shortened from Rate 4/5)5 896 15656 2493 1847 212 32108 727 13399 3428 6120 2663 19471 230 26952 2025 27943 3039 2834 862 28895 376 21106 2034 22867 951 20688 3108 35429 307 14210 2272 11971 1800 32802 331 23083 465 25524 1038 24795 1383 3436 94 2367 2619 1218 1497 27749 2116 18550 722 15841 2767 18812 2701 16103 3283 17324 168 10995 3074 2436 3460 9457 2049 17468 566 14279 3545 1168

TABLE 6Address of Parity Bit Accumulators (Shortened from Rate 5/6)3 2409 499 1481 908 559 716 1270 333 2508 2264 1702 28054 2447 19265 414 12246 2114 8427 212 5730 2383 21121 2286 23482 545 8193 1264 1434 1701 22585 964 1666 114 24137 2243 810 1245 15811 775 1692 1696 11043 1914 28314 532 14505 91 9746 497 22287 2326 15790 2482 2561 1117 12612 1257 16583 1478 12254 2511 9805 2320 26756 435 12787 228 5030 1885 23691 57 4832 838 10503 1231 19904 1738 685 2392 9516 163 6457 2644 1704

TABLE 7Address of Parity Bit Accumulators (Rate 8/9)0 1558 712 8051 1450 873 13372 1741 1129 11843 294 806 15664 482 605 9230 926 15781 777 13742 608 1513 1195 2104 1484 6920 427 4881 828 11242 874 13663 1500 8354 1496 5020 1006 17011 1155 972 657 14033 1453 6244 429 14950 809 3851 367 1512 1323 2023 960 3184 1451 10390 1098 17221 1015 14282 1261 15643 544 11904 1472 12460 508 6301 421 17042 284 8983 392 5774 1155 5560 631 10001 732 13682 1328 3293 1515 5064 1104 1172

TABLE 8Address of Parity Bit Accumulators (Rate 1/3)416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 69128978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 35753383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 22912797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 54206110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 43061505 5682 77787172 6830 66237281 3941 350510270 8669 9143622 7563 93889930 5058 45544844 9609 27076883 3237 17144768 3878 1001710127 3334 8267

TABLE 9Address of Parity Bit Accumulators (Shortened from Rate 1/5)6295 9626 304 7695 4839 4936 1660 144 11203 5567 6347 1255710691 4988 3859 3734 3071 3494 7687 10313 5964 8069 8296 1109010774 3613 5208 11177 7676 3549 8746 6583 7239 12265 2674 429211869 3708 5981 8718 4908 10650 6805 3334 2627 10461 9285 111207844 3079 107733385 10854 57471360 12010 122026189 4241 23439840 12726 4977

TABLE 10Address of Parity Bit Accumulators (Rate 2/5)5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 66585696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 80163992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 19314108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 22544247 888 4367 8821 9660 324 5864 4774 227 7889 6405 89639693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 31341652 8171 14353366 6543 37459286 8509 46457397 5790 89726597 4422 17999276 4041 38478683 7378 49465348 1993 91866724 9015 56464502 4439 84745107 7342 94421387 8910 2660

2. A method according to claim 1, wherein a Bose Chaudhuri Hocquenghem (BCH) outer code is used based on a generator polynomial of:

g(x)=(1+x+x³+x⁵+x¹⁴)×

(1+x⁶+x⁸+x¹¹+x¹⁴)×

(1+x+x²+x⁶+x⁹+x¹⁰+x¹⁴)×

(1+x⁴+x⁷+x⁸+x¹⁰+x¹²+x¹⁴)×

(1+x²+x⁵+x⁶+x⁷+x¹⁰+x¹¹+x¹³+x¹⁴)×

(1+x³+x⁷+x⁸+x⁹+x¹³+x¹⁴)×

(1+x²+x⁵+x⁶+x⁷+x¹⁰+x¹¹+x¹³+x¹⁴)×

(1+x⁵+x⁸+x⁹+x¹⁰+x¹¹+x¹⁴)×

(1+x+x²+x³+x⁹+x¹⁰+x¹⁴)×

(1+x³+x⁶+x⁹+x¹¹+x¹²+x¹⁴)×

(1+x⁴+x¹¹+x¹²+x¹⁴)×

(1+x+x²+x³+x⁵+x⁶+x⁷+x⁸+x¹⁰+x¹³+x¹⁴).

3. A method according to claim 1, further comprising:

modulating the LDPC coded signal; and

transmitting the modulated signal.

4. A method according to claim 3, wherein the modulated signal is transmitted over a satellite link in support of a broadband satellite application.

5. A method according to claim 3, wherein the modulating step is performed according to a signal constellation that includes one of 8-PSK (Phase Shift Keying), 16-QAM (Quadrature Amplitude Modulation), QPSK (Quadrature Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying) and 32-APSK.

6. A computer-readable medium bearing instructions for supporting transmission of a Low Density Parity Check (LDPC) coded signal, said instruction, being arranged, upon execution, to cause one or more processors to perform the method of claim 1.

7. An encoder for supporting transmission of a Low Density Parity Check (LDPC) coded signal, comprising:

means for receiving information bits; and

means for generating, based on the information bits, an Low Density Parity Check (LDPC) code according to one of Tables 1-10 for transmission as the LDPC coded signal, each of the Tables 1-10 specifying address of parity bit accumulators;

TABLE 1Address of Parity Bit Accumulators (Shortened from Rate 1/2)20 712 2386 6354 4061 1062 5045 515821 2543 5748 4822 2348 3089 6328 587622 926 5701 269 3693 2438 3190 350723 2802 4520 3577 5324 1091 4667 444924 5140 2003 1263 4742 6497 1185 62020 4046 69341 2855 662 6694 2123 3439 11584 3850 44225 5924 2906 1467 40497 7820 22428 4606 30809 4633 787710 3884 686811 8935 499612 3028 76413 5988 105714 7411 3450

TABLE 2Address of Parity Bit Accumulators (Rate 3/5)2765 5713 6426 3596 1374 4811 2182 544 3394 2840 4310 7714951 211 2208 723 1246 2928 398 5739 265 5601 5993 2615210 4730 5777 3096 4282 6238 4939 1119 6463 5298 6320 40164167 2063 4757 3157 5664 3956 6045 563 4284 2441 3412 63344201 2428 4474 59 1721 736 2997 428 3807 1513 4732 61952670 3081 5139 3736 1999 5889 4362 3806 4534 5409 6384 58095516 1622 2906 3285 1257 5797 3816 817 875 2311 3543 12054244 2184 5415 1705 5642 4886 2333 287 1848 1121 3595 60222142 2830 4069 5654 1295 2951 3919 1356 884 1786 396 47380 2161 26531 1380 14612 2502 37073 3971 10574 5985 60625 1733 60286 3786 19367 4292 9568 5692 34179 266 487810 4913 324711 4763 393712 3590 290313 2566 421514 5208 470715 3940 338816 5109 455617 4908 4177

TABLE 3Address of Parity Bit Accumulators (Rate 2/3)0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 26221 122 1516 3448 2880 1407 1847 3799 3529 373 971 4358 31082 259 3399 929 2650 864 3996 3833 107 5287 164 3125 23503 342 35294 4198 21475 1880 48366 3864 49107 243 15428 3011 14369 2167 251210 4606 100311 2835 70512 3426 236513 3848 247414 1360 17430 163 25361 2583 11802 1542 5093 4418 10054 5212 51175 2155 29226 347 26967 226 42968 1560 4879 3926 164010 149 292811 2364 56312 635 68813 231 168414 1129 3894

TABLE 4Address of Parity Bit Accumulators (Shortened from Rate 3/4)3 3198 478 4207 1481 1009 2616 1924 3437 554 683 18014 2681 21355 3107 40276 2637 33737 3830 34498 4129 20609 4184 274210 3946 107011 2239 9840 1458 30311 3003 13282 1137 17163 132 37254 1817 6385 1774 34476 3632 12577 542 36948 1015 19459 1948 41210 995 223811 4141 19070 2480 30791 3021 10882 713 13793 997 39034 2323 33615 1110 9866 2532 1427 1690 24058 1298 18819 615 17410 1648 311211 1415 2808

TABLE 5Address of Parity Bit Accumulators (Shortened from Rate 4/5)5 896 15656 2493 1847 212 32108 727 13399 3428 6120 2663 19471 230 26952 2025 27943 3039 2834 862 28895 376 21106 2034 22867 951 20688 3108 35429 307 14210 2272 11971 1800 32802 331 23083 465 25524 1038 24795 1383 3436 94 2367 2619 1218 1497 27749 2116 18550 722 15841 2767 18812 2701 16103 3283 17324 168 10995 3074 2436 3460 9457 2049 17468 566 14279 3545 1168

TABLE 6Address of Parity Bit Accumulators (Shortened from Rate 5/6)3 2409 499 1481 908 559 716 1270 333 2508 2264 1702 28054 2447 19265 414 12246 2114 8427 212 5730 2383 21121 2286 23482 545 8193 1264 1434 1701 22585 964 1666 114 24137 2243 810 1245 15811 775 1692 1696 11043 1914 28314 532 14505 91 9746 497 22287 2326 15790 2482 2561 1117 12612 1257 16583 1478 12254 2511 9805 2320 26756 435 12787 228 5030 1885 23691 57 4832 838 10503 1231 19904 1738 685 2392 9516 163 6457 2644 1704

TABLE 7Address of Parity Bit Accumulators (Rate 8/9)0 1558 712 8051 1450 873 13372 1741 1129 11843 294 806 15664 482 605 9230 926 15781 777 13742 608 1513 1195 2104 1484 6920 427 4881 828 11242 874 13663 1500 8354 1496 5020 1006 17011 1155 972 657 14033 1453 6244 429 14950 809 3851 367 1512 1323 2023 960 3184 1451 10390 1098 17221 1015 14282 1261 15643 544 11904 1472 12460 508 6301 421 17042 284 8983 392 5774 1155 5560 631 10001 732 13682 1328 3293 1515 5064 1104 1172

TABLE 8Address of Parity Bit Accumulators (Rate 1/3)416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 69128978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 35753383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 22912797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 54206110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 43061505 5682 77787172 6830 66237281 3941 350510270 8669 9143622 7563 93889930 5058 45544844 9609 27076883 3237 17144768 3878 1001710127 3334 8267

TABLE 9Address of Parity Bit Accumulators (Shortened from Rate 1/5)6295 9626 304 7695 4839 4936 1660 144 11203 5567 6347 1255710691 4988 3859 3734 3071 3494 7687 10313 5964 8069 8296 1109010774 3613 5208 11177 7676 3549 8746 6583 7239 12265 2674 429211869 3708 5981 8718 4908 10650 6805 3334 2627 10461 9285 111207844 3079 107733385 10854 57471360 12010 122026189 4241 23439840 12726 4977

TABLE 10Address of Parity Bit Accumulators (Rate 2/5)5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 66585696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 80163992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 19314108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 22544247 888 4367 8821 9660 324 5864 4774 227 7889 6405 89639693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 31341652 8171 14353366 6543 37459286 8509 46457397 5790 89726597 4422 17999276 4041 38478683 7378 49465348 1993 91866724 9015 56464502 4439 84745107 7342 94421387 8910 2660

8. An encoder according to claim 7, wherein a Bose Chaudhuri Hocquenghem (BCH) outer code is based on a generator polynomial of:

g(x)=(1+x+x³+x⁵+x¹⁴)×

(1+x⁶+x⁸+x¹¹+x¹⁴)×

(1+x+x²+x⁶+x⁹+x¹⁰+x¹⁴)×

(1+x⁴+x⁷+x⁸+x¹⁰+x¹²+x¹⁴)×

(1+x²+x⁵+x⁶+x⁷+x¹⁰+x¹¹+x¹³+x¹⁴)×

(1+x³+x⁷+x⁸+x⁹+x¹³+x¹⁴)×

(1+x²+x⁵+x⁶+x⁷+x¹⁰+x¹¹+x¹³+x¹⁴)×

(1+x⁵+x⁸+x⁹+x¹⁰+x¹¹+x¹⁴)×

(1+x+x²+x³+x⁹+x¹⁰+x¹⁴)×

(1+x³+x⁶+x⁹+x¹¹+x¹²+x¹⁴)×

(1+x⁴+x¹¹+x¹²+x¹⁴)×

(1+x+x²+x³+x⁵+x⁶+x⁷+x⁸+x¹⁰+x¹³+x¹⁴).

9. An encoder according to claim 7, further comprising:

means for modulating the LDPC coded signal; and

means for transmitting the modulated signal.

10. An encoder according to claim 9, wherein the modulated signal is transmitted over a satellite link in support of a broadband satellite application.

11. An encoder according to claim 9, wherein the modulating step is performed according to a signal constellation that includes one of 8-PSK (Phase Shift Keying), 16-QAM (Quadrature Amplitude Modulation), QPSK (Quadrature Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying) and 32-APSK.

12. A transmitter for supporting transmission of a Low Density Parity Check (LDPC) coded signal, comprising:

a Bose Chaudhuri Hocquenghem (BCH) encoder configured to receive information bits; and

a Low Density Parity Check (LDPC) encoder coupled to the BCH encoder for outputting, based on the information bits, an LDPC code having an outer BCH code according to one of Tables 1-10 for transmission as the LDPC coded signal, each of the Tables 1-10 specifying address of parity bit accumulators;

TABLE 1Address of Parity Bit Accumulators (Shortened from Rate 1/2)20 712 2386 6354 4061 1062 5045 515821 2543 5748 4822 2348 3089 6328 587622 926 5701 269 3693 2438 3190 350723 2802 4520 3577 5324 1091 4667 444924 5140 2003 1263 4742 6497 1185 62020 4046 69341 2855 662 6694 2123 3439 11584 3850 44225 5924 2906 1467 40497 7820 22428 4606 30809 4633 787710 3884 686811 8935 499612 3028 76413 5988 105714 7411 3450

TABLE 2Address of Parity Bit Accumulators (Rate 3/5)2765 5713 6426 3596 1374 4811 2182 544 3394 2840 4310 7714951 211 2208 723 1246 2928 398 5739 265 5601 5993 2615210 4730 5777 3096 4282 6238 4939 1119 6463 5298 6320 40164167 2063 4757 3157 5664 3956 6045 563 4284 2441 3412 63344201 2428 4474 59 1721 736 2997 428 3807 1513 4732 61952670 3081 5139 3736 1999 5889 4362 3806 4534 5409 6384 58095516 1622 2906 3285 1257 5797 3816 817 875 2311 3543 12054244 2184 5415 1705 5642 4886 2333 287 1848 1121 3595 60222142 2830 4069 5654 1295 2951 3919 1356 884 1786 396 47380 2161 26531 1380 14612 2502 37073 3971 10574 5985 60625 1733 60286 3786 19367 4292 9568 5692 34179 266 487810 4913 324711 4763 393712 3590 290313 2566 421514 5208 470715 3940 338816 5109 455617 4908 4177

TABLE 3Address of Parity Bit Accumulators (Rate 2/3)0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 26221 122 1516 3448 2880 1407 1847 3799 3529 373 971 4358 31082 259 3399 929 2650 864 3996 3833 107 5287 164 3125 23503 342 35294 4198 21475 1880 48366 3864 49107 243 15428 3011 14369 2167 251210 4606 100311 2835 70512 3426 236513 3848 247414 1360 17430 163 25361 2583 11802 1542 5093 4418 10054 5212 51175 2155 29226 347 26967 226 42968 1560 4879 3926 164010 149 292811 2364 56312 635 68813 231 168414 1129 3894

TABLE 4Address of Parity Bit Accumulators (Shortened from Rate 3/4)3 3198 478 4207 1481 1009 2616 1924 3437 554 683 18014 2681 21355 3107 40276 2637 33737 3830 34498 4129 20609 4184 274210 3946 107011 2239 9840 1458 30311 3003 13282 1137 17163 132 37254 1817 6385 1774 34476 3632 12577 542 36948 1015 19459 1948 41210 995 223811 4141 19070 2480 30791 3021 10882 713 13793 997 39034 2323 33615 1110 9866 2532 1427 1690 24058 1298 18819 615 17410 1648 311211 1415 2808

TABLE 5Address of Parity Bit Accumulators (Shortened from Rate 4/5)5 896 15656 2493 1847 212 32108 727 13399 3428 6120 2663 19471 230 26952 2025 27943 3039 2834 862 28895 376 21106 2034 22867 951 20688 3108 35429 307 14210 2272 11971 1800 32802 331 23083 465 25524 1038 24795 1383 3436 94 2367 2619 1218 1497 27749 2116 18550 722 15841 2767 18812 2701 16103 3283 17324 168 10995 3074 2436 3460 9457 2049 17468 566 14279 3545 1168

TABLE 6Address of Parity Bit Accumulators (Shortened from Rate 5/6)3 2409 499 1481 908 559 716 1270 333 2508 2264 1702 28054 2447 19265 414 12246 2114 8427 212 5730 2383 21121 2286 23482 545 8193 1264 1434 1701 22585 964 1666 114 24137 2243 810 1245 15811 775 1692 1696 11043 1914 28314 532 14505 91 9746 497 22287 2326 15790 2482 2561 1117 12612 1257 16583 1478 12254 2511 9805 2320 26756 435 12787 228 5030 1885 23691 57 4832 838 10503 1231 19904 1738 685 2392 9516 163 6457 2644 1704

TABLE 7Address of Parity Bit Accumulators (Rate 8/9)0 1558 712 8051 1450 873 13372 1741 1129 11843 294 806 15664 482 605 9230 926 15781 777 13742 608 1513 1195 2104 1484 6920 427 4881 828 11242 874 13663 1500 8354 1496 5020 1006 17011 1155 972 657 14033 1453 6244 429 14950 809 3851 367 1512 1323 2023 960 3184 1451 10390 1098 17221 1015 14282 1261 15643 544 11904 1472 12460 508 6301 421 17042 284 8983 392 5774 1155 5560 631 10001 732 13682 1328 3293 1515 5064 1104 1172

TABLE 8Address of Parity Bit Accumulators (Rate 1/3)416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 69128978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 35753383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 22912797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 54206110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 43061505 5682 77787172 6830 66237281 3941 350510270 8669 9143622 7563 93889930 5058 45544844 9609 27076883 3237 17144768 3878 1001710127 3334 8267

TABLE 9Address of Parity Bit Accumulators (Shortened from Rate 1/5)629596263047695483949361660144112035567634712557106914988385937343071349476871031359648069829611090107743613520811177767635498746658372391226526744292118693708598187184908106506805333426271046192851112078443079107733385108545747136012010122026189424123439840127264977

TABLE 10Address of Parity Bit Accumulators (Rate 2/5)565041438750583672080716351767134469227386658569616853207415701950235608260585769151770801639927712190725889707792180218666137884188619314108378175776810932282265396586744288827776622544247888436788219660324586447742277889640589639693500252022271811933019285140403048248063134165281711435336665433745928685094645739757908972659744221799927640413847868373784946534819939186672490155646450244398474510773429442138789102660

13. A transmitter according to claim 12, wherein the BCH outer code is based on a generator polynomial of:

g(x)=(1+x+x³+x⁵+x¹⁴)×

(1+x⁶+x⁸+x¹¹+x¹⁴)×

(1+x+x²+x⁶+x⁹+x¹⁰+x¹⁴)×

(1+x⁴+x⁷+x⁸+x¹⁰+x¹²+x¹⁴)×

(1+x²+x⁵+x⁶+x⁷+x¹⁰+x¹¹+x¹³+x¹⁴)×

(1+x³+x⁷+x⁸+x⁹+x¹³+x¹⁴)×

(1+x²+x⁵+x⁶+x⁷+x¹⁰+x¹¹+x¹³+x¹⁴)×

(1+x⁵+x⁸+x⁹+x¹⁰+x¹¹+x¹⁴)×

(1+x+x²+x³+x⁹+x¹⁰+x¹⁴)×

(1+x³+x⁶+x⁹+x¹¹+x¹²+x¹⁴)×

(1+x⁴+x¹¹+x¹²+x¹⁴)×

(1+x+x²+x³+x⁵+x⁶+x⁷+x⁸+x¹⁰+x¹³+x¹⁴).

14. A transmitter according to claim 12, further comprising:

a modulator configured to modulate the LDPC coded signal.

15. A transmitter according to claim 14, wherein the modulated signal is transmitted over a satellite link in support of a broadband satellite application.

16. A transmitter according to claim 14, wherein the modulating step is performed according to a signal constellation that includes one of 8-PSK (Phase Shift Keying), 16-QAM (Quadrature Amplitude Modulation), QPSK (Quadrature Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying) and 32-APSK.