Method for arranging circuit elements in semiconductor components

• US 20050066299A1
• Filed: 05/14/2004
• Published: 03/24/2005
• Est. Priority Date: 05/15/2003
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Wagner, Michael
• Application Number:
  US10/845,763
• Publication Number:
  US 20050066299A1
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

The problem of the invention, which concerns a method for arranging circuit elements in semiconductor components, in which according to a circuit draft, using a standard cell library, a physical layout is produced, in which the circuit elements are placed in the layout, one after the other, with their components, and with this layout, the circuit elements are structured in the semiconductor component, wherein each of the circuit elements has a driver, to which a driver strength is established, and connecting elements, is to indicate a method with which a placing of the circuit elements can be undertaken in such a way that a functionally reliable timing can be purposefully attained. This is attained in that the sensitivity of the circuit elements for a parasitic electromagnetic influencing is evaluated and in that the circuit elements with the highest sensitivity—that is, the susceptibility for parasitic influencing—are first placed with the shortest possible connecting elements.

Claims

1. Method for arranging circuit elements in semiconductor elements, in which according to a circuit draft, using a standard cell library, a physical layout is produced, in which the circuit which the circuit elements are placed in the layout, one after the other, with their components, and with this layout, the circuit elements are structured in the semiconductor component, wherein each of the circuit elements has a driver, to which a driver strength is established, and connecting elements, wherein the sensitivity of the circuit elements for a parasitic influencing is evaluated and in that the circuit elements with a highest sensitivity are placed with the shortest possible connecting elements.

2. Method according to claim 1, wherein the sensitivities of all circuit elements are determined, and the circuit elements with lower sensitivity are placed before circuit elements with a greater sensitivity.

3. Method according to claim 1, wherein the driver strength is used as a measure of the sensitivity.

4. Method according to claim 3, wherein network names of the circuit elements are stored with a marking of the respective driver strength.

5. Method according to claim 4, wherein a placing rank is calculated from the driver strength, and the placing elements are placed in accordance with the placing rank.

6. A method of forming a semiconductor device, the method comprising:

providing a circuit diagram that includes a number of circuit elements that arc interconnected with one another, each circuit element including a driver;

determining a driver strength for the driver of each circuit element;

evaluating a sensitivity for each of the circuit elements, the sensitivity being related to a susceptibility to parasitic influencing; and

determining a physical layout for the circuit elements, the physical layout including electrical connections to and from ones of the circuit elements wherein a physical length of each electrical connection is determined based on the sensitivity of a circuit element that is connected to that electrical connection.

7. The method of claim 6 wherein the circuit elements comprise circuit elements selected from a standard cell library.

8. The method of claim 6 wherein determining a physical layout comprises placing each of the circuit elements one by one.

9. The method of claim 8 wherein ones of the circuit elements with lower sensitivity are placed before ones of the circuits with a higher sensitivity.

10. The method of claim 6 wherein evaluating a sensitivity comprises evaluating a sensitivity based on driver strength.

11. The method of claim 6 and further comprising generating a table, the table including a network name for each circuit element along with a driver strength for each network name.

12. The method of claim 11 and further comprising determining a placing rank from each driver strength, wherein determining a physical layout comprising placing each circuit element one by one in an order determined by the placing rank.

13. The method of claim 6 and further comprising manufacturing a semiconductor device based on the physical layout.

14. A method of forming a semiconductor device, the method comprising:

providing a circuit diagram that includes a number of interconnected circuit elements;

determining a drive strength for each circuit element;

determining a physical layout location for a first circuit element that has a lowest drive strength;

determining a physical layout location for a second circuit element that has a second to lowest drive strength; and

continuing to determine physical layout locations for each other element, the physical layout locations being determined in an order determined by drive strength wherein the location of circuit elements with a lower drive strength are determined before the location of circuit elements with a higher drive strength.

15. The method of claim 14 and further comprising fabricating a semiconductor device in accordance with the physical layout.

16. The method of claim 15 w*wherein the circuit elements comprising circuit elements selected from a standard cell library.

17. The method of claim 16 and further comprising generating a table, the table comprising a network name for each circuit element along with a driver strength for each network name.

18. The method of claim 14 wherein the circuit elements comprising circuit elements selected from a standard cell library.

19. The method of claim 14 and further comprising generating a table, the table comprising a network name for each circuit element along with a driver strength for each network name.

20. The method of claim 19 wherein the circuit elements comprising circuit elements selected from a standard cell library.