Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

• US 20050067620A1
• Filed: 08/09/2004
• Published: 03/31/2005
• Est. Priority Date: 09/30/2003
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Victor, Ieong, Meikei, Guarini, Kathryn W.
• Application Number:
  US10/914,433
• Publication Number:
  US 20050067620A1
• Time in Patent Office: Days
• US Class Current: 257/67
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

Claims

1-19. -19. (Cancelled)

20. A three dimensional (3D) integrated circuit comprising:

a first interconnect structure comprising at least a first semiconductor device located on a surface of a first Si-containing layer of a first silicon-on-insulator substrate, said first Si-containing layer having a first surface orientation that is optimal for said first semiconductor device;

a second interconnect structure comprising at least a second semiconductor device that differs from the first semiconductor device located on a surface of a second Si-containing layer of a second silicon-on-insulator substrate, said second Si-containing layer having a second surface orientation that is optimal for said second semiconductor device; and

vertical interconnects connecting the first interconnect structure to the second interconnect structure.

21. The 3D integrated circuit of claim 20 wherein the first semiconductor device is a pFET, the first Si-containing layer has a (110) crystallographic orientation, the second semiconductor device is an nFET, and the second Si-containing layer has a (100) crystallographic orientation.

22. The 3D integrated circuit of claim 20 wherein the first semiconductor device is an nFET, the first Si-containing layer has a (100) crystallographic orientation, the second semiconductor device is a pFET, and the second Si-containing layer has a (110) crystallographic orientation.

23. The 3D integrated circuit of claim 20 wherein said first and second interconnect structure comprise at least a patterned interconnect dielectric having conductive wiring located therein.

24. The 3D integrated circuit of claim 20 wherein said first and second Si-containing layers comprise Si, SiGe, SiC, SiGeC, Si/Si, Si/SiGe, Si/SiGeC or any other semiconductor material that includes silicon.

25. The 3D integrated circuit of claim 20 wherein said first and second silicon-on-insulators each comprise a buried insulating layer beneath said Si-containing layers.

26. The 3D integrated circuit of claim 25 wherein said buried insulating layer is continuous.

27. The 3D integrated circuit of claim 25 wherein said buried insulating layer is non-continuous.

28. The 3D integrated circuit of claim 25 wherein said buried insulating layer has a thickness from about 10 to about 1000 nm.

29. The 3D integrated circuit of claim 28 wherein said thickness is from about 100 to about 200 nm.

30. The 3D integrated circuit of claim 20 wherein said first and second Si-containing layers each have a thickness from about 20 to about 200 nm.

31. The 3D integrated circuit of claim 30 wherein said thickness is from about 50 to about 100 nm.

32. The 3D integrated circuit of claim 20 wherein said first semiconductor device and said second semiconductor device are both field effect transistors.

33. The 3D integrated circuit of claim 20 wherein said first interconnect structure and said second interconnect structure are joined together with a polymeric adhesive.