Semiconductor device containing stacked semiconductor chips and manufacturing method thereof

• US 20050067682A1
• Filed: 09/28/2004
• Published: 03/31/2005
• Est. Priority Date: 09/30/2003
• Status: Abandoned Application

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Usui, Ryosuke, Mizuhara, Hideki, Nakamura, Takeshi
• Application Number:
  US10/952,203
• Publication Number:
  US 20050067682A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48475 connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85051 Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

Stacked interconnect layers each of which includes an interlayer dielectric film and an interconnect line made of copper, and solder resist layer formed as the top layer constitute a multilevel interconnect configuration. The first element, the second element and a circuit element are mounted on the surface of the configuration. The second element bonds to the first element by an adhesion layer. The upper surface of the first element is treated by plasma, and the second element is mounted on the surface.

Claims

1. A semiconductor device comprising:

a first semiconductor chip; and

a second semiconductor chip mounted on the first semiconductor chip, wherein an upper surface of the first semiconductor chip is a plasma treatment surface, and the second semiconductor chip is mounted on the plasma treatment surface.

2. The semiconductor device of claim 1, wherein the plasma treatment surface comprises a surface of the first semiconductor chip.

3. The semiconductor device of claim 1, wherein the plasma treatment surface comprises a surface of an adhesion layer formed on the first semiconductor chip.

4. The semiconductor device of claim 1, wherein the plasma treatment surface comprises a back side surface of a semiconductor substrate on the first semiconductor chip.

5. The semiconductor device of claim 1, wherein the first semiconductor chip is mounted on an upper surface of a dielectric film, and the plasma treatment surface comprises the upper surface of the dielectric film.

6. The semiconductor device of claim 5, wherein the dielectric film is comprised of a melamine derivative.

7. The semiconductor device of claim 5, wherein the upper surface of the dielectric film has a cluster of micro projections.

8. The semiconductor device of claim 1, wherein the first semiconductor chip is mounted on an upper surface of a metal interconnect line, and the plasma treatment surface comprises the upper surface of the metal interconnect line.

9. The semiconductor device of claim 1, further comprising a base material provided with a conductor circuit, wherein at least a part of the conductor circuit is exposed on a underside surface of the base material, wherein the first semiconductor chip and the second semiconductor chip are formed on an upper side of the base material.

10. A manufacturing method of a semiconductor device comprising:

forming a first semiconductor chip on a base material;

performing plasma treatment for a surface of the base material and an upper surface of the first semiconductor chip; and

forming a second semiconductor chip on the upper surface of the first semiconductor chip, which is treated by the plasma.

11. The manufacturing method of a semiconductor device of claim 10, wherein the plasma treatment is implemented by using a plasma gas comprising an inert gas and with no bias voltage applied to the base material.

12. The manufacturing method of a semiconductor device of claim 10, wherein the plasma treatment is implemented to a surface comprising a surface of the first semiconductor chip.

13. The manufacturing method of a semiconductor device of claim 10 further comprising forming an adhesion layer on an upper surface of the first semiconductor chip before the plasma treatment, wherein the plasma treatment is implemented to a surface comprising a surface of the adhesion layer.

14. The manufacturing method of a semiconductor device of claim 10, wherein the first semiconductor chip, which is mounted on a semiconductor substrate, is formed on the base material so that the semiconductor substrate is located in an upper side, and the plasma treatment is implemented for an backside surface of the semiconductor substrate.

15. The manufacturing method of a semiconductor device of claim 10, wherein the surface of the base material comprises an upper surface of a dielectric film.

16. The manufacturing method of a semiconductor device of claim 15, wherein the dielectric film is comprised of a melamine derivative.

17. The manufacturing method of a semiconductor device of claim 15, wherein a cluster of micro projections are formed on the upper surface of the dielectric film by the plasma treatment.

18. The manufacturing method of a semiconductor device of claim 10, wherein the surface of the base material comprises an upper surface of a metal interconnect line.