Plasma surface modification and passivation of organo-silicate glass films for improved hardmask adhesion and optimal RIE processing

• US 20050067702A1
• Filed: 09/30/2003
• Published: 03/31/2005
• Est. Priority Date: 09/30/2003
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dalton, Timothy, Kumar, Kaushik, America, William, Wickland, Heidi
• Application Number:
  US10/674,646
• Publication Number:
  US 20050067702A1
• Time in Patent Office: Days
• US Class Current: 257/753
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

Interconnect structure having enhanced adhesion between the various interfaces encompassing an organo-silicate glass (OSG) film, for use in semiconductor devices is provided herein. The novel interconnect structure includes a non-damaged plasma-treated low-k OSG surface to enhance the adhesion of the hardmask material to the OSG surface, and an unique deposition scheme for the hardmasks in order to make the entire structure pliant towards implementing mild processing condition during the reactive ion etch patterning of the dielectric structure in a damascene and dual-damascene scheme. The methods for making a semiconductor device having an enhanced adhesion and micromasks free profiles are also provided.

Claims

1. An interconnect structure comprising:

one or more interconnect levels, one on top of each other, each level comprising a organo-silicate glass (OSG) dielectric material having a plasma treated surface layer that provides improved adhesion to an overlying lower hardmask, yet is substantially undamaged.

2. The interconnect structure of claim 1 wherein the OSG dielectric material comprises a non-porous or porous material having a dielectric constant less than 3.

3. The interconnect structure of claim 1 wherein the OSG dielectric material comprises a combination of porous and non-porous OSG materials.

4. The interconnect structure of claim 1 wherein the OSG dielectric material comprises a material of Si, C, O and H and having a dielectric constant less than about 3.

5. The interconnect structure of claim 4 wherein the OSG dielectric material comprises about 10 to about 40 atomic (at.) % Si, about 10 to about 40 at. % C, about 15 to about 45 at. % O, and about 20 to about 50 at. % H.

6. The interconnect structure of claim 1 further comprising a dielectric cap layer beneath said OSG dielectric material.

7. The interconnect structure of claim 1 wherein the lower hardmask comprises a dielectric material of Si, C, O and H and having a dielectric constant less than about 5.

8. The interconnect structure of claim 1 wherein the lower hardmask comprises of a dielectric material of Si, C, O, H and N and having a dielectric constant less than about 5.

9. The interconnect structure of claim 1 wherein the adhesion improved by greater than 15%.

10. The interconnect structure of claim 1 further comprising an upper hardmask located atop said lower hardmask.

11. The interconnect structure of claim 10 wherein said lower hardmask does not include a densified surface layer.

12. A method of forming an interconnect structure comprising:

plasma treating an OSG dielectric layer to provide a plasma-treated OSG surface layer that provides improved adhesion to an overlying lower hardmask, said plasma-treated OSG surface layer is chemically and electrical unaltered from the bulk of the OSG dielectric layer; and

forming said lower hardmask atop the plasma-treated OSG surface layer.

13. The method of claim 12 wherein the plasma treatment is performed in H₂ or He, at a plasma power of less than about 200 W and a plasma exposure of less than about 10 sec.

14. The method of claim 12 wherein the plasma treating causes a variation in the dielectric constant of the OSG dielectric of less than 0.05.

15. The method of claim 12 wherein the lower hardmask is formed in-situ.

16. The method of claim 12 further comprising forming an upper hardmask atop the lower hardmask.

17. The method of claim 16 wherein the upper hardmask is formed in-situ thereby avoiding the need for densifying the lower hardmask prior to upper hardmask deposition.

18. The method of claim 17 wherein the absence of densifying leads to a reduction in micromask formation during a subsequent reactive ion etch step.

19. A method of forming an interconnect structure comprising:

providing an integrated circuit that includes a dielectric cap layer located thereon;

forming an organo-silicate glass (OSG) dielectric layer on said dielectric cap layer; and

plasma treating the OSG dielectric layer to provide a plasma-treated OSG surface layer that provides improved adhesion to an overlying lower hardmask, said plasma-treated OSG surface layer is chemically and electrical unaltered from the bulk of the OSG dielectric layer;

in-situ forming said lower hardmask atop the plasma-treated OSG surface layer; and

in-situ forming an upper hardmask atop said lower hardmask.