Event signature apparatus, systems, and methods

• US 20050068187A1
• Filed: 09/30/2003
• Published: 03/31/2005
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shahidzadeh, Shahrokh, Douglas, Jonathan P., Kumar, Anil V.
• Granted Patent: US 7,557,725 B2
• Time in Patent Office: Days
• US Class Current: 340/635
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206

Abstract

An apparatus and a system, as well as a method and article, may operate to compare a circuit operational condition with a specified condition, to record an out-of-specification condition, and to determine some specified number of recorded out-of-specification conditions.

Claims

1. A method, comprising:

storing at least one over-voltage condition occurring in an integrated circuit in a non-volatile memory.

2. The method of claim 1, further comprising:

determining a specified number of stored over-voltage conditions.

3. The method of claim 2, further comprising:

indicating the specified number of stored over-voltage conditions.

4. A method, comprising:

comparing a operational condition with a specified condition;

recording an out-of-specification condition; and

determining a specified number of recorded out-of-specification conditions.

5. The method of claim 4, further comprising:

detecting the out-of-specification condition as an over-voltage condition.

6. The method of claim 4, further comprising:

refraining from detecting the out-of-specification condition for a specified amount of time.

7. The method of claim 6, wherein the specified amount of time is associated with a power-on reset time.

8. The method of claim 4, wherein the specified condition comprises a recommended operational voltage upper limit associated with an integrated circuit.

9. The method of claim 4, wherein recording the out-of-specification condition further comprises:

recording the out-of-specification condition in a non-volatile memory.

10. The method of claim 9, wherein the non-volatile memory is indelible.

11. The method of claim 4, wherein determining the specified number of recorded out-of-specification conditions further comprises:

reading a signature value stored in a non-volatile memory.

12. An article comprising a machine-accessible medium having associated data, wherein the data, when accessed, results in a machine performing:

comparing an operational voltage with a specified voltage;

recording an over-voltage condition; and

determining a specified number of recorded over-voltage conditions.

13. The article of claim 12, wherein the data, when accessed, results in the machine performing:

filtering the operational voltage for at least a duration of one clock period.

14. The article of claim 12, wherein recording the over-voltage condition further comprises:

recording the over-voltage condition only if the operational voltage is greater than the specified voltage by a selected amount.

15. The article of claim 14, wherein the selected amount is at least about two times greater than an expected noise voltage value.

16. The article of claim 12, wherein the data, when accessed, results in the machine performing:

verifying recordation of the over-voltage condition.

17. An apparatus, comprising:

an indelible memory to store a selected number of out-of-specification operational conditions encountered by an electronic circuit.

18. The apparatus of claim 17, further comprising:

a detection module coupled to the indelible memory to determine the existence of at least one of the selected number of out-of-specification operational conditions.

19. The apparatus of claim 18, further comprising:

a filter module coupled to the detection module.

20. The apparatus of claim 17, wherein the indelible memory comprises a fuse.

21. The apparatus of claim 17, wherein at least one of the out-of-specification operational conditions comprises an over-voltage condition.

22. A system, comprising:

an indelible memory to store a selected number of out-of-specification operational conditions encountered by an electronic circuit; and

a display coupled to the electronic circuit.

23. The system of claim 22, wherein the electronic circuit comprises a microprocessor.

24. The system of claim 22, further comprising:

a logic module to detect each one of the selected number of out-of-specification operational conditions.

25. The system of claim 24, wherein the logic module comprises an analog-to-digital converter.

26. The system of claim 22, further comprising:

a memory to store a specified condition to be compared with an operational condition associated with the electronic circuit.

27. The system of claim 26, wherein the specified condition comprises a recommended operational voltage upper limit associated with an integrated circuit.

28. The system of claim 27, wherein the integrated circuit comprises a microprocessor.

29. The system of claim 22, further comprising:

a basic input-output system to determine the selected number of out-of-specification operational conditions.