Digital compensation of excess delay in continuous time sigma delta modulators

• US 20050068213A1
• Filed: 07/29/2004
• Published: 03/31/2005
• Est. Priority Date: 09/25/2003
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mohieldin, Ahmed Nader, Fontaine, Paul-Aymeric
• Application Number:
  US10/903,608
• Publication Number:
  US 20050068213A1
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: H03M 3/37 Compensation or reduction of delay or phase error
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/45 with distributed feedforward inputs, i.e. with forward paths from the modulator input to more than one filter stage
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Abstract

A continuous time sigma delta modulator having minimal excess loop delay. The continuous-time sigma delta modulator in accordance with the present invention includes at least one integrator stage coupled to receive an input signal and a resultant integrator output signal from a previous stage for providing a resultant integrator output. At least one output stage connects to the at least one integrator stage to receive the resultant integrator output signal from the previous integrator stage for providing a resultant integrator output. A sample and hold circuit connects to receive the second integrator input signal. A multiplier connects to the sample and hold circuit to provide a resultant sampled signal. An analog-to-digital converter quantizer couples to receive the resultant sampled signal and to produce a quantized output signal. A digital modulation loop circuit connects to the analog-to-digital converter quantizer to generate a resultant quantized output signal for correcting excess loop delay in the continuous time sigma delta modulator. A fourth feedback multiplier coupled to receive the resultant quantized output signal and produce a second resultant quantized output signal. A digital-to-analog converter coupled to receive the second resultant quantized output signal to produce a modulation feedback signal. A delay connects to the digital-to-analog converter to receive the modulation feedback signal and provide the resultant modulation feedback signal

Claims

1. A continuous time sigma delta modulator, comprising:

at least one integrator stage coupled to receive an input signal and a resultant integrator output signal from a previous stage for providing a resultant integrator output;

at least one output stage coupled to receive the resultant integrator output signal from a previous at least one integrator stage for providing a resultant integrator output;

a sample and hold circuit coupled to receive the second integrator input signal to sample and hold the second integrator input signal;

a multiplier coupled to the sample and hold circuit to provide a resultant sampled signal;

an analog-to-digital converter quantizer coupled to receive the resultant sampled signal and to produce a quantized output signal;

a digital modulation loop circuit coupled to the analog-to-digital converter quantizer to generate a resultant quantized output signal for correcting excess loop delay in the continuous time sigma delta modulator;

a fourth feedback multiplier coupled to receive the resultant quantized output signal and produce a second resultant quantized output signal;

a digital-to-analog converter coupled to receive the second resultant quantized output signal to produce a modulation feedback signal; and

a delay coupled to the digital-to-analog converter to receive the modulation feedback signal and provide the resultant modulation feedback signal.

2. A continuous time sigma delta modulator as recited in claim 1, wherein the at least one integrator stage comprises:

an input multiplier coupled to receive the input signal to generate a resultant input signal,

a feedback multiplier coupled to receive a modulation feedback signal to generate a resultant modulation feedback signal;

an adder to calculate an integrator input signal as a difference between the resultant input signal, the resultant integrator output signal from the previous stage, and the resultant modulation feedback signal;

a continuous time integrator coupled to receive the integrator input signal to integrate and produce an integrator output signal having a common mode component; and

an integrator multiplier coupled to receive the integrator output signal to provide the resultant integrator output signal.

3. A continuous time sigma delta modulator as recited in claim 1, wherein the at least one output stage comprises:

an first input multiplier coupled to receive the input signal to generate a resultant input signal;

a feedback multiplier coupled to receive a modulation feedback signal to generate a resultant modulation feedback signal;

a first adder to calculate a first integrator input signal as a difference between the resultant input signal, the resultant integrator output signal from the previous stage, and the resultant modulation feedback signal;

a continuous time integrator coupled to receive the first integrator input signal to integrate and produce an integrator output signal having a common mode component;

an integrator multiplier coupled to receive the integrator output signal to provide the resultant integrator output signal;

a second input multiplier coupled to receive the input signal to generate a second resultant input signal; and

a second adder to calculate a second integrator input signal as a difference between the second resultant input signal and the resultant integrator output signal.

4. A apparatus as recited in claim 1, wherein the digital modulation loop circuit comprises,

an adder coupled to receive the quantized output signal and a second modulated feedback signal to generate a resultant quantized output signal;

a delay coupled to receive the resultant quantized output signal; and

a feedback multiplier coupled to receive the delayed resultant quantized output signal to provide the second modulated feedback signal.