Display device, method of driving the same and electric equipment

• US 20050068279A1
• Filed: 09/21/2004
• Published: 03/31/2005
• Est. Priority Date: 09/25/2003
• Status: Active Grant

• Current Assignee: Japan Display East Incorporated (Japan Display Incorporated)
• Original Assignee: Hitachi Displays Limited (Japan Display Incorporated)
• Inventors: Hirota, Shoichi, Kaneko, Hiroki, Komura, Shinichi, Edo, Susumu, Sugita, Tatsuya, Funahata, Katsuyuki, Oshima, Tetsuya
• Granted Patent: US 7,859,527 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/2077 by a combination of two or more gradation control methods
• CPC Class Codes: G09G 3/3433 using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices using liquid crystal devices G09G3/36; using electrochromic devices G09G3/38
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A reference voltage line is synchronously scanned with scanning of a scanning signal line, voltage of the reference voltage line is set to be the voltage of a common electrode, the second transistor is set to be OFF state during the reference voltage line is set in the common voltage for a pixel wherein a node between an image signal memory and said second transistor is set in a voltage so that said second transistor becomes OFF and the voltage of image signal line is set to be high voltage level when the voltage of the scanning signal line changes from low voltage level to high voltage level for the pixel wherein the node between the image signal memory and the second transistor is set in a voltage so that said second transistor becomes ON.

Claims

1. A method for driving a display device which has plural pixels aligned in a matrix form on a substrate,

each of which pixels has at least a first transistor, a second transistor, an image signal memory, an electro optic medium and a common electrode and is connected to at least an image signal line, a scanning signal line and a reference voltage line, wherein either a drain or a source and a rest of said source or said drain of said first transistor are respectively connected to said image signal line and a gate of said second transistor,

a gate of said first transistor is connected said scanning signal line,

either said drain or said source and a rest of said source or said drain of said second transistor are respectively connected to said electro optic medium and said reference voltage line, and

said image signal memory is connected to said gate of said second transistor and said common electrode,

the method including a step that scanning of said reference voltage line is carried out synchronous with scanning of said scanning signal line.

2. A method according to claim 1, wherein

a scanning interval for said image signal memory to be refreshed and a image signal holding period during when an image signal written in said image signal memory is held are prepared;

and

voltage of said reference voltage line is kept to be a common voltage for a predetermined term synchronously with scanning of said scanning signal line in said scanning interval and driving waveform of said reference voltage line is kept to be a square wave form having a certain frequency in a term other than said predetermined term.

3. A method according to claim 2, wherein

in a selecting term to select said scanning signal line, voltage of said reference voltage line corresponding to said scanning line is set to be a common voltage and wherein

a reset period to initialize a voltage difference between both terminals of said electro optic medium and an image signal writing period to write a image signal to said image signal memory are prepared;

and

said voltage of said image signal line is set to be high voltage level in said reset period and said voltage of said image signal line is set to be high voltage level or low voltage level-in response to said image signal in said image signal writing period.

4. A method according to claim 2, wherein

voltage of said reference voltage line is set to said common voltage synchronously with scanning of said scanning signal line;

voltage of said image signal line is set high voltage level in a constant time during said reference voltage line is in said common voltage for a pixel wherein a node between said image signal memory and said gate of said second transistor is set in a voltage so that said second transistor becomes OFF state; and

voltage of said image signal line is set high voltage level at a same moment that said scanning is switched from high voltage level to low voltage level for a pixel wherein a node between said image signal memory and said second transistor is set a voltage so that said second transistor becomes on.

5. A method according to claim 2, wherein

voltage of said reference voltage line is set to said common voltage synchronously with scanning of said scanning signal line;

voltage of said image signal line is set high voltage level in a constant time during said reference voltage line is in said common voltage for a pixel wherein a node between said image signal memory and said second transistor is set in a voltage so that said second transistor becomes OFF state; and

voltage of said image signal line is set high voltage level just before said scanning is switched from high voltage level to low voltage level for a pixel wherein a node between said image signal memory and said second transistor is set in a voltage so that said second transistor becomes on.

6. A method according to a Claim selected from any one of claims 3 to 5, wherein

a scanning interval to scan said scanning signal lines and image holding period to hold status of said image display by stopping scanning said scanning signal lines are set;

and

said scanning signal line is set a voltage so that said second transistor is off during said image holding period.

7. A display device which has plural pixels aligned in a matrix form on a substrate,

each of which pixels has at least a first transistor, a second transistor, an image signal memory, an electro optic medium and a common electrode is connected to at least a signal, a scanning signal line and a reference voltage line, wherein

either a drain or a source and a rest of said source or said drain of said first transistor are respectively connected to said signal line and a gate of said second transistor;

a gate of said first transistor is connected to said scanning signal line;

either said drain or said a source and a rest of said source or said drain of said second transistor are respectively connected to said electro optic medium and said reference voltage line; and

said image signal memory is connected to said gate of said second transistor and said common electrode, and

has a reference voltage line drive circuitry which scans said reference voltage line synchronously with scanning of said scanning signal line.

8. A display device according to claim 7, wherein said image signal memory is composed of at least two wiring layers and one insulation layer.

9. A display device according to claim 7, wherein

said electro optic medium is made of insulation solvent;

and

charged particles are dispersed in said insulation solvent.

10. A display device according to claim 7, wherein

said pixels are all consist of sub-pixels having two kinds of sizes which characterize planar areas in a ratio of m²+1:

1.

11. A display device according to claim 8, wherein

said image signal memory is constructed with a transparent electrode connected to said reference voltage line;

a source electrode of said first transistor and said insulation layer set therebetween; and

said transparent electrode extends to outside of a region occupied by-all said pixels to form an electrical connecting terminal in outside of said substrate.

12. An electrophoretic display which is constructed with an active matrix substrate and a transparent substrate with a predetermined gap which has insulation solvent and charged particles are dispersed therein, wherein

each pixel constructed in said active matrix substrate has a reflective electrode and said transparent substrate has a patterned electrode in a predetermined shape.

13. An electrophoretic display according to claim 12, wherein

an insulation wall is constructed at a boundary of said each pixel so that said insulation solvent and said charged particles are separated for said each pixel;

and

said insulation wall at least overlays on a portion of said patterned electrode in a predetermined shape.

14. An electrophoretic display according to claim 13, wherein said insulation wall is made of photo resin.

23. A method according to claim 13, wherein a light shielding layer is formed between a grating-shaped electrode and said transparent substrate.

24. A method according to claim 13, wherein an organic transparent insulation film is formed between said grating-shaped electrode and said insulation wall.

25. A method according to claim 13 to drive said electrophoretic display device, wherein

said insulation wall is formed on said transparent substrate;

and

said grating-shaped electrode is formed so that a portion of said grating-shaped electrode overlays said insulation wall.

26. A method according to claim 25, wherein a protection layer is formed on at least either said transparent electrode or said active matrix substrate.

27. A method according to claim 13, wherein said insulation solvent and said charged particles dispersed in said insulation solvent are formed by printing process.

42. An electrophoretic display according to any one of claims 12 and 40, wherein said reflective electrode has a corrugation structure.

43. An electrophoretic display according to claim 42, wherein

said corrugation structure is formed at least by corrugation forming layer and a leveling layer;

and

said leveling layer is formed by black-colored resin layer.

44. An electrophoretic display according to claim 43, wherein said leveling layer is formed with a transparent resin layer and a black-colored resin layer.

15. A method for driving an electrophoretic display device which has plural pixels aligned in a matrix form on a substrate,

each of which pixels have at least a first transistor, a second transistor, an image signal memory, an electro optic medium and a common electrode is connected to at least a signal, a scanning signal line and a reference voltage line, wherein either a drain or a source and a rest of a source or a drain of said first transistor are respectively connected to said signal line and a gate of said second transistor,

a gate of said first transistor is connected to said scanning signal line,

either a drain or a source and a rest of said source or said drain of said second transistor are respectively connected to said electro optic medium and said reference voltage line, and

said image signal memory is connected to said gate of said second transistor and said common electrode,

the method including a step that scanning of said reference voltage line is carried out synchronously with scanning of said scanning signal line.

16. A method according to claim 15, wherein

said a scanning interval for updating display images by refreshing said image signal memory and a image signal holding period during when an image signal written in said image signal memory is held are prepared;

and

voltage of said reference voltage line is kept to be one of voltages given by a group of a common voltage and a specific voltage for a predetermined term synchronously with scanning of said scanning signal line in said scanning interval and driving waveform of said reference voltage line is kept to be a predetermined voltage being different from said common voltage and said specific voltage in a term other than said predetermined term.

17. A method according to claim 16, wherein

said refreshing of said image signal memory and said updating of display images are carried out during at least two of said scanning intervals as voltage of said reference voltage line is set to be a reset voltage synchronously with scanning of said scanning signal line in one of said scanning intervals and voltage of said reference voltage line is set to said common voltage synchronously with scanning of said scanning signal line in another one of said scanning intervals.

18. A method according to claim 17, wherein

a selecting term to select a certain scanning signal line is prepared during which term a reset term during when voltage of a certain reference voltage line corresponding to a certain scanning line is set to be one of voltages given by a group of said common voltage and said reset voltage and voltage difference between both terminals of said electro optic medium is initialized and a image signal writing period during when image signal is written in said image signal memory are prepared;

voltage of said image signal line is set to be high voltage level in said reset term; and

voltage of said image signal line is set to be high voltage level or low voltage level in response to said image signal.

19. A method according to claim 17, wherein

voltage of said reference voltage line is set to be one of voltages given by a group of said common voltage and reset voltage synchronously with scanning of said scanning signal line;

voltage of said image signal line is set high voltage level in a constant time during said reference voltage line is in one of voltages given by a group of said common voltage and said reset voltage for a pixel wherein a node between said image signal memory and said second transistor is set in a voltage so that said second transistor becomes OFF state; and

voltage of said image signal line is set high voltage level when said scanning is switched from high voltage level to low voltage level for a pixel wherein a node between image signal memory and said second transistor is set in a voltage so that said second transistor becomes on.

20. A method according to claim 17, wherein

voltage of said reference voltage line is set to be one of voltages given by a group of said common voltage and reset voltage synchronously with scanning of said scanning signal line;

voltage of said image signal line is set high voltage level in a constant time during said reference voltage line is in one of voltages given by a group of said common voltage and said reset voltage for a pixel wherein a node between said image signal memory and said second transistor is set in a voltage so that said second transistor becomes OFF state; and

voltage of said image signal line is set to low voltage level from high voltage level just before said scanning is switched from high voltage level to low voltage level for a pixel wherein a node between said image signal memory and said second transistor is set in a voltage so that said second transistor becomes on.

21. A method according to claim 16, wherein

voltage of said reference voltage line is set to be said common voltage for a constant term after set to be said reset voltage synchronously with scanning of said scanning signal line for a constant term;

voltage of said image signal line is set high voltage level in a constant time during said reference voltage line is in one of voltages given by a group of said common voltage and said reset voltage for a pixel wherein a node between said image signal memory and said second transistor is set in a voltage so that said second transistor becomes OFF state; and

voltage of said image signal line is set high voltage level when said scanning is switched from high voltage level to low voltage level for a pixel wherein a node between image signal memory and said second transistor is set in a voltage so that said second transistor becomes on.

22. A method according to any one of claims 18 to 21, wherein

a scanning interval to scan said scanning signal lines and image holding period to hold status of image display by stopping scanning said scanning signal lines are set;

and said scanning signal line is set in a voltage so that said second transistor is off during said image holding period.

28. A display device which has plural pixels aligned in a matrix form on a substrate,

each of which pixels have at least a first transistor, a second transistor, an image signal memory, an electro optic medium and a common electrode and is connected to at least a signal, a scanning signal line and a reference voltage line,

wherein either a drain or a source and a rest of said source or said drain of said first transistor are respectively connected to said image signal line and a gate of said second transistor;

a gate of said first transistor is connected to said scanning signal line;

either a drain or a source and a rest of said source or said drain of said second transistor are respectively connected to said electro optic medium and said reference voltage line; and

said image signal memory is connected to said gate of said second transistor and said common electrode, and

said electro optic medium has a memory capability in displaying images.

29. A display device according to claim 28, wherein

said electro optic medium is made of insulation solvent;

and

charged particles are dispersed in said insulation solvent.

30. A display device according to claim 28, wherein said electro optic medium is made of a material which can reversibly colored or bleached by means of applying voltage.

31. A display device according to claim 28, wherein said electro optic medium is made of a cholesteric liquid crystal material.

32. A method for driving a display device which has plural pixels aligned in a matrix form on a substrate,

each of which pixels has at least a first transistor, a second transistor, an image signal memory, an electro optic medium and a common electrode and is connected to at least a signal, a scanning signal line and a reference voltage line,

wherein either a drain or a source and a rest of said source or said drain of said first transistor are respectively connected to said image signal line and a gate of said second transistor;

a gate of said first transistor is connected to said scanning signal line;

either a drain or a source and a rest of said source or said drain of said second transistor are respectively connected to said electro optic medium and said reference voltage line;

said image signal memory is connected to said gate of said second-transistor and said common electrode; and

said electro optic medium is connected to said drain or said source of said second transistor and said common electrode,

the method including a step that said electro optic medium is rewritten on image display status by changing voltage between said drain or said source of said second transistor and said common electrode.

33. A method according to claim 32, wherein voltage of said reference voltage line sequentially takes at least three different voltages including a voltage similar to a voltage of said common electrode.

34. A method according to claim 32, wherein said electro optic medium has at least two image display status which are independently written in said electro optic medium in two scanning intervals.

35. A method according to claim 32, wherein a scanning interval to set said second transistor in OFF state is prepared.

36. A method according to claim 32, wherein voltages of pixel electrodes of all of said pixels which are effective for image display are set to be a voltage similar to voltage of said common electrode at an end of an scanning interval to scan said scanning signal line.

37. A method according to claim 32, wherein voltage of said reference voltage line is set to be a voltage similar to said common electrode in a scanning interval when said second transistor is set to be OFF state.

38. A method according to claim 37, wherein scanning of said reference voltage line is carried out synchronously with scanning of said signal scanning line.

39. An electrophoretic display which is constructed with an active matrix substrate and a transparent substrate with a predetermined gap which has insulation solvent and charged particles are dispersed therein, wherein

each pixel constructed in said active matrix substrate has a reflective electrode;

an insulation wall is constructed at a boundary of said each pixel so that said insulation solvent and said charged particles are separated for said each pixel and that a plurality of said insulation walls conform a patterned insulation wall; and

a patterned common electrode and a patterned black matrix are formed in layers on said patterned electrode in a predetermined shape.

40. An electrophoretic display according to claim 39, wherein

an ink material is coated on an ink transfer body which has a property of ink repellency;

and

said patterned common electrode or said patterned black matrix are formed by selectively transferring said ink material.

41. An electrophoretic display according to claim 40, wherein an electrode to outwardly extend said patterned common electrode is formed on side wall of said patterned common electrode.