CMOS imaging system with low fixed pattern noise

• US 20050068439A1
• Filed: 02/11/2004
• Published: 03/31/2005
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Innovative Technology Licensing LLC
• Inventors: Loose, Markus, Kozlowski, Lester J.
• Granted Patent: US 7,046,284 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence
• CPC Class Codes: H03F 3/082 with FET's H03F3/085 takes precedence
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A CMOS imager system comprising an active pixel sensor having an access supply which provides distributed feedback, a column buffer (having gain and FPN suppression), and an A/D converter co-located with the sensor such that the effective transmission path between the column buffer (or optional analog PGA) and the A/D converter acts as a resistor, rather than a reactance. The system may further include both an analog gain amplifier stage and a digital programmable amplifier stage.

Claims

1. A CMOS imager system comprising:

an active pixel sensor;

a column buffer connected to the active pixel sensor; and

an analog-to-digital (A/D) converter co-located with the active pixel sensor and column buffer, such that a transmission path between the column buffer and the A/D converter acts primarily as a resistance, rather than a reactance.

2. The CMOS imager system of claim 1, further comprising an analog programmable gain amplifier connected between the column buffer and the A/D converter, such that a transmission path between the analog programmable gain amplifier and the A/D converter acts primarily as a resistance, rather than a reactance.

3. The CMOS imager system of claim 2, wherein the active pixel sensor comprises an access supply, a tapered reset supply and a source supply.

4. The CMOS imager system of claim 3, wherein the A/D converter is a high-speed converter have 12 bit or greater resolution.

5. The CMOS imager system of claim 4, wherein the column buffer has gain and fixed-pattern noise (FPN) suppression.

6. The CMOS imager system of claim 5, wherein the analog programmable gain amplifier has tunable electronic bandwidth.

7. A digital video system comprising:

an active pixel sensor;

a column buffer connected to receive an output from the active pixel sensor;

an analog programmable gain amplifier connected to the column buffer;

an analog-to-digital (A/D) converter connected to the analog programmable gain amplifier and co-located with the active pixel sensor, column buffer and analog programmable gain amplifier, such that a transmission path between the analog gain amplifier and the A/D converter acts primarily as a resistance, rather than a reactance;

a digital programmable gain amplifier connected to an output of the A/D converter; and

a digital video interface connected to an output of the digital programmable gain amplifier.

8. The digital video system of claim 7, wherein the active pixel sensor comprises an access supply, a tapered reset supply and a source supply.

9. The digital video system of claim 8, wherein the A/D converter is a high-speed converter have 12 bit or greater resolution.

10. The digital video system of claim 9, wherein the column buffer has gain and fixed-pattern noise (FPN) suppression.

11. The digital video system of claim 10, wherein the analog programmable gain amplifier has tunable electronic bandwidth.