Overvoltage protection circuit of output MOS transistor

• US 20050068705A1
• Filed: 09/24/2004
• Published: 03/31/2005
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Nakahara, Akihiro
• Granted Patent: US 7,576,964 B2
• Time in Patent Office: Days
• US Class Current: 361/100
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

An overvoltage protection circuit is for a circuit of an output MOS transistor and a load connected in series between a first power supply and a second power supply. The overvoltage protection circuit contains a control signal circuit, a dynamic clamping circuit, a control switch, and a serge detecting circuit. The control signal circuit is connected between a gate of said output MOS transistor and said load, and the dynamic clamping circuit is connected with said gate of said output MOS transistor. The control switch is connected between said first power supply and said dynamic clamping circuit and the serge detecting circuit which monitors a voltage of said first power supply and turns on said control switch when the voltage of said first power supply increases to a voltage higher than a predetermined voltage.

Claims

1. An overvoltage protection circuit for a circuit of an output MOS transistor and a load connected in series between a first power supply and a second power supply, comprising:

a dynamic clamping circuit connected with said gate of said output MOS transistor;

a control switch connected between said first power supply and said dynamic clamping circuit; and

a serge detecting circuit which monitors a voltage of said first power supply and turns on said control switch when the voltage of said first power supply increases to a voltage higher than a predetermined voltage.

2. The overvoltage protection circuit according to claim 1, further comprising:

a control signal circuit connected between a gate of said output MOS transistor and said load;

3. The overvoltage protection circuit according to claim 2, wherein said control signal circuit comprises:

a first resistance connected at a first end with said gate of said output MOS transistor, a second end of said first resistance being supplied a first control signal; and

a discharge switch connected between said second end of said first resistance and said a node between said output MOS transistor and said load,

said output MOS transistor is turned on in response to said first control signal of a first logic level, and is turned off in response to said first control signal of a second logic level,

said discharge switch is turned on when said output MOS transistor is turned off, such that a charge of said gate of said output MOS transistor is discharged through said first resistance, and said discharge switch is turned off when said output MOS transistor is turned on.

4. The overvoltage protection circuit according to claim 1, wherein said serge detecting circuit comprises:

a first diode which has a cathode connected with said first power supply and breaks down when the voltage of said first power supply increases to the voltage higher than the predetermined voltage;

a second resistance connected between an anode of said first diode and a third power supply;

a first inverter which inverts a logic level corresponding to a voltage at a node between said first diode and said second resistance; and

a second inverter which inverts an output of said first inverter such that said control switch is turned on when said first diode is broken down.

5. The overvoltage protection circuit according to claim 1, wherein said dynamic clamping circuit comprises:

a zener diode which has a cathode connected with said first power supply; and

a diode connected between an anode of said zener diode and said gate of said output MOS transistor.

6. The overvoltage protection circuit according to claim 1, wherein said output MOS transistor is formed by connecting a plurality of unit cell transistors in parallel, and has a second breakdown characteristic in a safe operation area.

7. A method of protecting an output MOS transistor, wherein said output MOS transistor and a load are connected in series between a first power supply and a second power supply, and a series circuit of a control switch and a dynamic clamping circuit is connected between said first power supply and a gate of said output MOS transistor, said method comprising:

monitoring a voltage of said first power supply;

turning off a control switch when the voltage of said first power supply increases to a voltage higher than a predetermined voltage.

8. The method according to claim 7, wherein said load is an inductive load,

said method further comprises:

disconnecting said gate of said output MOS transistor from a drain of said output MOS transistor when said output MOS transistor is turned on; and

connecting said gate of said output MOS transistor and said drain of said output MOS transistor through a resistance when said output MOS transistor is turned off, such that a charge of said gate of said output MOS transistor is discharged through said resistance.

9. The overvoltage protection circuit according to claim 7, wherein said monitoring comprises:

setting a voltage of a first node to a high voltage when the voltage of said first power supply does not increase to the voltage higher than the predetermined voltage; and

setting a voltage of the first node to a low voltage when the voltage of said first power supply increases to the voltage higher than the predetermined voltage,

said turning off a control switch comprises;

turning off said control switch based on the low voltage of the first node.