System and method for digital radio receiver
First Claim
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1. A communications system, comprising:
- a processor;
a variable oscillator;
a radio frequency (RF) quadrature demodulator;
a variable capacitor, coupled to the RF quadrature demodulator output;
a continuous-time, sigma-delta analog-to-digital converter (ADC), coupled between the processor and the RF quadrature mixer; and
a frequency divider, coupled to the processor, the variable oscillator, the RF quadrature demodulator, and the ADC;
wherein the processor, the variable oscillator, the frequency divider, the RF quadrature demodulator, the variable capacitor, and the ADC are integrated on a single, semiconductor chip;
wherein the ADC samples an output of the RF quadrature demodulator; and
wherein the processor sets a frequency of the communications system by controlling the variable oscillator, the frequency divider and the variable capacitor.
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Abstract
A communications system comprising a processor, a variable oscillator, a radio frequency (RF) quadrature demodulator, a variable capacitor, a continuous-time, sigma-delta analog-to-digital converter (ADC), and a frequency divider, all integrated on a single semiconductor chip. The ADC samples the RF quadrature demodulator output. The processor sets the communications system frequency by controlling the oscillator, the frequency divider and the variable capacitor.
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Citations
22 Claims
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1. A communications system, comprising:
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a processor;
a variable oscillator;
a radio frequency (RF) quadrature demodulator;
a variable capacitor, coupled to the RF quadrature demodulator output;
a continuous-time, sigma-delta analog-to-digital converter (ADC), coupled between the processor and the RF quadrature mixer; and
a frequency divider, coupled to the processor, the variable oscillator, the RF quadrature demodulator, and the ADC;
wherein the processor, the variable oscillator, the frequency divider, the RF quadrature demodulator, the variable capacitor, and the ADC are integrated on a single, semiconductor chip;
wherein the ADC samples an output of the RF quadrature demodulator; and
wherein the processor sets a frequency of the communications system by controlling the variable oscillator, the frequency divider and the variable capacitor. - View Dependent Claims (2, 3)
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4. A communications system, comprising:
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a continuous-time, sigma-delta analog-to-digital converter (ADC); and
a processor, the processor monitoring a magnitude of a received signal and controlling communications system gain in response to the magnitude of the received signal;
wherein the ADC input circuitry comprises a plurality of transconductance amplifiers coupled in parallel with one another;
wherein control of the communications system gain comprises adjusting the gain of the ADC by selectively enabling one or more of the plurality of transconductance amplifiers; and
wherein the processor and the ADC are integrated on a single, semiconductor chip. - View Dependent Claims (5, 6)
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7. A communications system, comprising:
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a processor;
a radio frequency (RF) quadrature demodulator, coupled to the processor; and
a variable capacitor, coupled to the demodulator output and to the processor;
wherein the processor, the RF quadrature demodulator, and the variable capacitor are integrated on a single, semiconductor chip;
wherein the variable capacitor and output circuitry of the RF quadrature demodulator form a tunable, low-pass filter; and
wherein the processor sets the pole frequency of the tunable, low-pass filter. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A method, usable in a single-chip digital radio frequency (RF) receiver comprising an RF quadrature demodulator coupled to a plurality of continuous-time, sigma-delta analog-to-digital converters, comprising:
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demodulating the in-phase (I) and quadrature (Q) baseband signals;
digitizing the I and Q baseband signals;
averaging digitized I and Q data;
reducing a sampling frequency of the digitized I and Q data to the Nyquist frequency for the I and Q baseband signals;
eliminating DC-offsets in the digitized I and Q data;
estimating a combined, weighted magnitude of the digitized I and Q data;
averaging and integrating the combined, weighted magnitude of the digitized I and Q data;
generating one or more gain control signals based on an averaged and integrated value of the combined, weighted magnitude of the digitized I and Q data;
controlling gain of a plurality of amplification stages within the single-chip, digital RF receiver; and
stepping the gain of each of the plurality of amplification stages by predetermined discrete values;
wherein the gain of each of the plurality of amplification stages is stepped in response to the combined, weighted magnitude of the digitized I and Q data so as to strive to maintain the output of the single-chip digital RF receiver within a predetermined range of magnitudes. - View Dependent Claims (16, 17)
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18. A communications system, comprising:
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a power supply having a supply node and a return node; and
an amplifier having an input node and an output node, the amplifier comprising;
a first metal oxide semiconductor (MOS) device having a drain coupled to a current-injection node, a source coupled to the return node of the power supply, and a gate coupled to the input node of the amplifier;
a load resistor coupled between the output node of the amplifier and the supply node of the power supply;
a second MOS device having a source coupled to the current-injection node, a drain coupled to the output node of the amplifier, and a coupled to a bias voltage source; and
a constant current source coupled to the supply node of the power supply and the current-injection node;
wherein the current source provides a bleed current sufficient to operate the first MOS device linearly for a given value of the load resistor.
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19. A communications system, comprising:
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a means for receiving a radio frequency (RF) signal;
a means for amplifying the received RF signal, the means for amplifying divided into a plurality of individual means for amplifying; and
a means for averaging an estimated magnitude of a demodulated signal;
wherein the gain of each of the plurality of individual means for amplifying is independently controllable; and
wherein the means for controlling increases or decreases the gain of each of the plurality of individual means for amplifying by predetermined discrete values;
- View Dependent Claims (20)
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21. A single-chip communications system, comprising:
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a means for receiving a signal of a maximum voltage not exceeding an operating voltage of a high voltage, metal oxide semiconductor (MOS) device integrated on the single-chip communications system;
a means for amplifying a received, high voltage signal;
a means for mixing an amplified, high voltage signal with a signal from a local oscillator of a maximum voltage not exceeding an operating voltage of a low voltage, MOS device integrated on the single-chip communications system; and
a means for filtering the mixed, high voltage signal;
wherein the single-chip communications system receives a quadrature modulated radio frequency signal at its input; and
wherein the single-chip communications system outputs a demodulated, digital signal.
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22. A single-chip communications system, comprising:
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a means for receiving a signal of a maximum voltage not exceeding an operating voltage of a low voltage, metal oxide semiconductor (MOS) device integrated on the single-chip communications system;
a means for amplifying a received, low voltage signal;
a means for mixing an amplified signal, of a maximum voltage not exceeding an operating voltage of a high voltage MOS device, with a signal from a local oscillator of a maximum voltage not exceeding an operating voltage of a low voltage, MOS device integrated on the single-chip communications system; and
a means for filtering the mixed, high voltage signal;
wherein the single-chip communications system receives a quadrature modulated radio frequency signal at its input; and
wherein the single-chip communications system outputs a demodulated, digital signal.
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Specification