System and method for digital radio receiver

• US 20050070325A1
• Filed: 08/10/2004
• Published: 03/31/2005
• Est. Priority Date: 09/25/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bellaouar, Abdellatif, Fontaine, Paul-Aymeric
• Granted Patent: US 7,376,400 B2
• Time in Patent Office: Days
• US Class Current: 455/550.100
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A communications system comprising a processor, a variable oscillator, a radio frequency (RF) quadrature demodulator, a variable capacitor, a continuous-time, sigma-delta analog-to-digital converter (ADC), and a frequency divider, all integrated on a single semiconductor chip. The ADC samples the RF quadrature demodulator output. The processor sets the communications system frequency by controlling the oscillator, the frequency divider and the variable capacitor.

Claims

1. A communications system, comprising:

a processor;

a variable oscillator;

a radio frequency (RF) quadrature demodulator;

a variable capacitor, coupled to the RF quadrature demodulator output;

a continuous-time, sigma-delta analog-to-digital converter (ADC), coupled between the processor and the RF quadrature mixer; and

a frequency divider, coupled to the processor, the variable oscillator, the RF quadrature demodulator, and the ADC;

wherein the processor, the variable oscillator, the frequency divider, the RF quadrature demodulator, the variable capacitor, and the ADC are integrated on a single, semiconductor chip;

wherein the ADC samples an output of the RF quadrature demodulator; and

wherein the processor sets a frequency of the communications system by controlling the variable oscillator, the frequency divider and the variable capacitor.

2. The communication system of claim 1, wherein output circuitry of the RF quadrature demodulator and the variable capacitor form a tunable, single-pole, low-pass filter.

3. The communications system of claim 1, further comprising an RF low-noise amplifier (LNA) coupled to the input of the RF quadrature demodulator, wherein the RF LNA is integrated on the single, semiconductor chip.

4. A communications system, comprising:

a continuous-time, sigma-delta analog-to-digital converter (ADC); and

a processor, the processor monitoring a magnitude of a received signal and controlling communications system gain in response to the magnitude of the received signal;

wherein the ADC input circuitry comprises a plurality of transconductance amplifiers coupled in parallel with one another;

wherein control of the communications system gain comprises adjusting the gain of the ADC by selectively enabling one or more of the plurality of transconductance amplifiers; and

wherein the processor and the ADC are integrated on a single, semiconductor chip.

5. The communications system of claim 4, further comprising a variable gain amplifier (VGA), wherein control of the communications system gain further comprises adjusting the VGA gain in discrete steps.

6. The communications system of claim 5, wherein the VGA is integrated on the single, semiconductor chip.

7. A communications system, comprising:

a processor;

a radio frequency (RF) quadrature demodulator, coupled to the processor; and

a variable capacitor, coupled to the demodulator output and to the processor;

wherein the processor, the RF quadrature demodulator, and the variable capacitor are integrated on a single, semiconductor chip;

wherein the variable capacitor and output circuitry of the RF quadrature demodulator form a tunable, low-pass filter; and

wherein the processor sets the pole frequency of the tunable, low-pass filter.

8. The communications system of claim 7, wherein the tunable, low-pass filter is a single-pole filter.

9. The communications system of claim 7, wherein an input amplifier of the RF quadrature demodulator comprises a common-gate amplifier.

10. The communications system of claim 7, wherein the variable capacitor comprises a plurality of fixed capacitors coupled together through one or more switches, the one or more switches coupled to and controlled by the processor.

11. The communications system of claim 10, wherein the plurality of fixed capacitors can be selectively combined together in parallel by operating each of the one or more switches.

12. The communications system of claim 10, wherein the plurality of fixed capacitors can be selectively combined together in series by operating each of the one or more switches.

13. The communications system of claim 10, wherein the plurality of fixed capacitors can be selectively combined together in parallel and in series by operating each of the one or more switches.

14. The communications system of claim 10, wherein the fixed capacitors are metal oxide semiconductor (MOS) capacitors, biased to operate in an accumulation region of the MOS capacitor.

15. A method, usable in a single-chip digital radio frequency (RF) receiver comprising an RF quadrature demodulator coupled to a plurality of continuous-time, sigma-delta analog-to-digital converters, comprising:

demodulating the in-phase (I) and quadrature (Q) baseband signals;

digitizing the I and Q baseband signals;

averaging digitized I and Q data;

reducing a sampling frequency of the digitized I and Q data to the Nyquist frequency for the I and Q baseband signals;

eliminating DC-offsets in the digitized I and Q data;

estimating a combined, weighted magnitude of the digitized I and Q data;

averaging and integrating the combined, weighted magnitude of the digitized I and Q data;

generating one or more gain control signals based on an averaged and integrated value of the combined, weighted magnitude of the digitized I and Q data;

controlling gain of a plurality of amplification stages within the single-chip, digital RF receiver; and

stepping the gain of each of the plurality of amplification stages by predetermined discrete values;

wherein the gain of each of the plurality of amplification stages is stepped in response to the combined, weighted magnitude of the digitized I and Q data so as to strive to maintain the output of the single-chip digital RF receiver within a predetermined range of magnitudes.

16. The method of claim 15, wherein control of each of the plurality of amplification stages is exercised sequentially such that the gain of stages electrically closest to the front-end of the single-chip digital RF receiver is stepped up before stages electrically further away from the front-end of the single-chip digital RF receiver.

17. The method of claim 15, wherein control of each of the plurality of amplification stages is exercised sequentially such that the gain of stages electrically furthest away from the front-end of the single-chip digital RF receiver is stepped down before stages closest to the front-end of the single-chip digital RF receiver.

18. A communications system, comprising:

a power supply having a supply node and a return node; and

an amplifier having an input node and an output node, the amplifier comprising;

a first metal oxide semiconductor (MOS) device having a drain coupled to a current-injection node, a source coupled to the return node of the power supply, and a gate coupled to the input node of the amplifier;

a load resistor coupled between the output node of the amplifier and the supply node of the power supply;

a second MOS device having a source coupled to the current-injection node, a drain coupled to the output node of the amplifier, and a coupled to a bias voltage source; and

a constant current source coupled to the supply node of the power supply and the current-injection node;

wherein the current source provides a bleed current sufficient to operate the first MOS device linearly for a given value of the load resistor.

19. A communications system, comprising:

a means for receiving a radio frequency (RF) signal;

a means for amplifying the received RF signal, the means for amplifying divided into a plurality of individual means for amplifying; and

a means for averaging an estimated magnitude of a demodulated signal;

wherein the gain of each of the plurality of individual means for amplifying is independently controllable; and

wherein the means for controlling increases or decreases the gain of each of the plurality of individual means for amplifying by predetermined discrete values;

20. The communications system of claim 19, wherein the gain of each of the plurality of individual means for amplifying is automatically increased or decreased in a predetermined order, in response to the value estimated by the means for averaging, maintaining the signal magnitude at each of the plurality of individual means for amplifying within a predetermined range of operation.

21. A single-chip communications system, comprising:

a means for receiving a signal of a maximum voltage not exceeding an operating voltage of a high voltage, metal oxide semiconductor (MOS) device integrated on the single-chip communications system;

a means for amplifying a received, high voltage signal;

a means for mixing an amplified, high voltage signal with a signal from a local oscillator of a maximum voltage not exceeding an operating voltage of a low voltage, MOS device integrated on the single-chip communications system; and

a means for filtering the mixed, high voltage signal;

wherein the single-chip communications system receives a quadrature modulated radio frequency signal at its input; and

wherein the single-chip communications system outputs a demodulated, digital signal.

22. A single-chip communications system, comprising:

a means for receiving a signal of a maximum voltage not exceeding an operating voltage of a low voltage, metal oxide semiconductor (MOS) device integrated on the single-chip communications system;

a means for amplifying a received, low voltage signal;

a means for mixing an amplified signal, of a maximum voltage not exceeding an operating voltage of a high voltage MOS device, with a signal from a local oscillator of a maximum voltage not exceeding an operating voltage of a low voltage, MOS device integrated on the single-chip communications system; and

a means for filtering the mixed, high voltage signal;

wherein the single-chip communications system receives a quadrature modulated radio frequency signal at its input; and

wherein the single-chip communications system outputs a demodulated, digital signal.