PSEUDO-RANDOM BINARY SEQUENCE CHECKER WITH AUTOMATIC SYNCHRONIZATION

• US 20050071399A1
• Filed: 09/26/2003
• Published: 03/31/2005
• Est. Priority Date: 09/26/2003
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Haar, Allen P., Bonaccio, Anthony R.
• Granted Patent: US 7,219,113 B2
• Time in Patent Office: Days
• US Class Current: 708/250
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31728 Optical aspects, e.g. opto-electronics used for testing, optical signal transmission for testing electronic circuits, electro-optic components to be tested in combination with electronic circuits, measuring light emission of digital circuits probes having electro-optic elements G01R1/071; electro-optic sampling for oscilloscopes G01R13/347; contactless testing of individual semiconductor devices by optical means G01R31/2656
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G06F 2207/582 Parallel finite field implementation, i.e. at least partially parallel implementation of finite field arithmetic, generating several new bits or trits per step, e.g. using a GF multiplier
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register

Abstract

A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.

Claims

1. A parallel pseudo-random binary sequence checker comprising:

circuitry capable of receiving a pseudo-random binary sequence in parallel n-bit sample, wherein said pseudo-random binary sequence is generated by a pseudo-random binary sequence generator;

circuitry capable of automatically synchronizing the state of said receiving means with an n-bit sample within said pseudo-random binary sequence to provide a next n-bit sample within said pseudo-random binary sequence; and

circuitry capable of comparing said next n-bit sample within said pseudo-random binary sequence to said next received n-bit sample within said pseudo-random binary sequence, wherein said comparing means indicates an error condition occurred if said next n-bit sample within said pseudo-random binary sequence does not equal to said next received n-bit sample within said pseudo-random binary sequence.

2. The checker of claim 1, wherein said checker further includes

a plurality of latches and a plurality of XOR gates connected to a subset of said plurality of latches;

circuitry capable of loading 16 most significant bits to said checker;

circuitry capable of loading 15 least significant bits to said checker; and

circuitry capable of serially advancing said plurality of latches twice.

3. The checker of claim 1, wherein said checker further includes a multiplexor for yielding output bits in parallel.

4. The checker of claim 1, wherein said checker further includes a mask register.

5. The checker of claim 1, wherein said checker further includes an error window start register and an error window end register coupled to an error counter.

6. The checker of claim 1, wherein said checker further includes a sync detect start register, a sync detect end register, a sync detect threshold register and a sync detector.

10. The method of claim 1, wherein said method further includes providing a mask register for masking specific bits in error.

11. The method of claim 1, wherein said method further includes providing an error counter to count a number of

errors occurred since said checker was previously reset.

12. The method of claim 1, wherein said method further includes providing a logical indication of an occurrent of a failed synchronization.

7. A method for synchronizing a parallel pseudo-random binary sequence checker, said method comprising:

receiving a pseudo-random binary sequence in parallel n-bit sample, wherein said pseudo-random binary sequence is generated by a pseudo-random binary sequence generator;

automatically synchronizing the state of said receiving means with an n-bit sample within said pseudo-random binary sequence to provide a next n-bit sample within said pseudo-random binary sequence; and

comparing said next n-bit sample within said pseudo-random binary sequence to said next received n-bit sample within said pseudo-random binary sequence, wherein said comparing means indicates an error condition occurred if said next n-bit sample within said pseudo-random binary sequence does not equal to said next received n-bit sample within said pseudo-random binary sequence.

8. The method of claim 7, wherein said method further includes

loading 16 most significant bits to said checker;

loading 15 least significant bits to said checker; and

serially advancing said plurality of latches twice.

9. The method of claim 7, wherein said method further includes providing a multiplexor for yielding output bits in parallel.