System and method for processor dedicated code handling in a multi-processor environment

• US 20050071513A1
• Filed: 09/25/2003
• Published: 03/31/2005
• Est. Priority Date: 09/25/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nutter, Mark Richard, Stafford, James Michael, Aguilar, Maximino Jr.
• Granted Patent: US 7,549,145 B2
• Time in Patent Office: Days
• US Class Current: 710/1
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

A system and method is provided to perform code handling, such as interpreting language instructions or performing “just-in-time” compilation using a heterogeneous processing environment that shares a common memory. In a heterogeneous processing environment that includes a plurality of processors, one of the processors is programmed to perform a dedicated code-handling task, such as perform just-in-time compilation or interpretation of interpreted language instructions, such as Java. The other processors request code handling processing that is performed by the dedicated processor. Speed is achieved using a shared memory map so that the dedicated processor can quickly retrieve data provided by one of the other processors.

Claims

1. A computer-implemented method for processing software code, said method comprising:

receiving, at a second processor, a code processing request requested by a first processor, wherein the first and second processors are heterogeneous processors within a computer system that share a common memory;

writing software code data corresponding to the request to a local memory corresponding to the second processor in response to the request; and

processing the software code data by the second processor.

2. The method as described in claim 1 further comprising:

prior to the receiving;

reading script code from the common memory;

writing the script code to a local memory corresponding to the first processor;

interpreting, at the first processor, the script code, the interpreting resulting in the software code; and

writing the software code to the second processor'"'"'s local memory.

3. The method as described in claim 1 further comprising:

writing data resulting from the executing to the common memory.

4. The method as described in claim 1 further comprising:

prior to the receiving;

running a first program, during the running of the first program, identifying a call to the software code; and

loading the software code into the common memory, wherein the processing of the software code is occurs simultaneously to the running of the first program and wherein the processing is completed prior to the call of the software code from the first program.

5. The method as described in claim 4 further comprising:

performing a multimedia effect resulting from the processing of the software code, the performance performed by the second processor.

6. The method as described in claim 4 further comprising:

receiving, at the first processor, executable instructions resulting from the processing performed by the second processor, wherein the executable instructions are adapted to perform a multimedia effect; and

performing the multimedia effect on the first processor by executing the received executable instructions.

7. The method as described in claim 1 further comprising:

loading, a the second processor, a virtual machine program into the second processor'"'"'s local memory;

reading, from the common memory shared by the first and second processors, the software code data that includes virtual machine code adapted to be processed by the virtual machine program;

processing the virtual machine code at the second processor using the virtual machine program, the processing resulting in executable instructions;

writing the executable instructions to a memory location accessible by the first processor using a DMA operation; and

executing, at the first processor, the executable instructions.

8. The method as described in claim 7 wherein the memory location is selected from the group consisting of a local memory corresponding to the first processor, and the common memory.

9. The method as described in claim 7 wherein the first and second processors are dislike processors with different instruction set architectures and wherein the executable instructions are adapted to be executed on the first processor and not the second processor.

10. The method as described in claim 1 wherein the processing results in one or more program instructions adapted to be performed by the first processor, the method further comprising:

writing the program instructions to the common memory;

notifying the first processor that the program instructions have been written; and

executing the program instructions by the first processor.

11. An information handling system comprising:

a plurality of heterogeneous processors;

a common memory shared by the plurality of heterogeneous processors;

a first processor selected from the plurality of processors that sends a code processing request to a second processor, the second processor also being selected from the plurality of processors;

a local memory corresponding to the second processor;

a DMA controller associated with the second processor, the DMA controller adapted to transfer data between the common memory and the second processor'"'"'s local memory; and

a processing tool for processing software code, the processing tool including software effective to;

receive, at a second processor, the code processing request requested by the first processor;

write software code data corresponding to the request to the second processor'"'"'s local memory in response to the request; and

process the software code data by the second processor.

12. The information handling system as described in claim 11 further comprising software code effective to:

prior to the reception of the request;

read script code from the common memory;

write the script code to a local memory corresponding to the first processor;

interpret, at the first processor, the script code, the interpreting resulting in the software code; and

write the software code to the second processor'"'"'s local memory.

13. The information handling system as described in claim 11 further comprising software code effective to:

write data resulting from the executing to the common memory.

14. The information handling system as described in claim 11 further comprising software code effective to:

prior to the reception of the request;

run a first program, during the running of the first program, identify a call to the software code; and

load the software code into the common memory, wherein the processing of the software code is occurs simultaneously to the running of the first program and wherein the processing of the software code is completed prior to the call of the software code from the first program.

15. The information handling system as described in claim 14 further comprising software code effective to:

perform a multimedia effect resulting from the processing of the software code, the performance performed by the second processor.

16. The information handling system as described in claim 14 further comprising software code effective to:

receive, at the first processor, executable instructions resulting from the processing performed by the second processor, wherein the executable instructions are adapted to perform a multimedia effect; and

perform the multimedia effect on the first processor by executing the received executable instructions.

17. The information handling system as described in claim 11 further comprising software code effective to:

load, a the second processor, a virtual machine program into the second processor'"'"'s local memory;

read, from the common memory shared by the first and second processors, the software code data that includes virtual machine code adapted to be processed by the virtual machine program;

process the virtual machine code at the second processor using the virtual machine program, the processing resulting in executable instructions;

write, using a DMA operation, the executable instructions to a memory location accessible by the first processor; and

execute, at the first processor, the executable instructions.

18. The information handling system as described in claim 17 wherein the memory location is selected from the group consisting of a local memory corresponding to the first processor, and the common memory.

19. The information handling system as described in claim 17 wherein the first and second processors are dislike processors with different instruction set architectures and wherein the executable instructions are adapted to be executed on the first processor and not the second processor.

20. The information handling system as described in claim 11 wherein the process results in one or more program instructions adapted to be performed by the first processor, the information handling system further comprising software code effective to:

write the program instructions to the common memory;

notify the first processor that the program instructions have been written; and

execute the program instructions by the first processor.

21. A computer program product stored on a computer operable media for processing software code, said computer program product comprising:

means for receiving, at a second processor, a code processing request requested by a first processor, wherein the first and second processors are heterogeneous processors within a computer system that share a common memory;

means for writing software code data corresponding to the request to a local memory corresponding to the second processor in response to the request; and

means for processing the software code data by the second processor.

22. The computer program product as described in claim 21 further comprising:

prior to the means for receiving;

means for reading script code from the common memory;

means for writing the script code to a local memory corresponding to the first processor;

means for interpreting, at the first processor, the script code, the interpreting resulting in the software code; and

means for writing the software code to the second processor'"'"'s local memory.

23. The computer program product as described in claim 21 further comprising:

means for writing data resulting from the executing to the common memory.

24. The computer program product as described in claim 21 further comprising:

prior to the means for receiving;

means for running a first program, during the running of the first program, identifying a call to the software code; and

means for loading the software code into the common memory, wherein the processing of the software code is occurs simultaneously to the running of the first program and wherein the processing is completed prior to the call of the software code from the first program.

25. The computer program product as described in claim 24 further comprising:

means for performing a multimedia effect resulting from the processing of the software code, the performance performed by the second processor.

26. The computer program product as described in claim 24 further comprising:

means for receiving, at the first processor, executable instructions resulting from the processing performed by the second processor, wherein the executable instructions are adapted to perform a multimedia effect; and

means for performing the multimedia effect on the first processor by executing the received executable instructions.

27. The computer program product as described in claim 21 further comprising:

means for loading, a the second processor, a virtual machine program into the second processor'"'"'s local memory;

means for reading, from the common memory shared by the first and second processors, the software code data that includes virtual machine code adapted to be processed by the virtual machine program;

means for processing the virtual machine code at the second processor using the virtual machine program, the processing resulting in executable instructions;

means for writing the executable instructions to a memory location accessible by the first processor using a DMA operation; and

means for executing, at the first processor, the executable instructions.

28. The computer program product as described in claim 27 wherein the memory location is selected from the group consisting of a local memory corresponding to the first processor, and the common memory.

29. The computer program product as described in claim 27 wherein the first and second processors are dislike processors with different instruction set architectures and wherein the executable instructions are adapted to be executed on the first processor and not the second processor.

30. The computer program product as described in claim 21 wherein the means for processing results in one or more program instructions adapted to be performed by the first processor, the computer program product further comprising:

means for writing the program instructions to the common memory;

means for notifying the first processor that the program instructions have been written; and

means for executing the program instructions by the first processor.