Processor power and energy management

• US 20050071701A1
• Filed: 09/30/2003
• Published: 03/31/2005
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Granted Patent: US 7,174,469 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30156 Special purpose encoding of instructions, e.g. Gray coding
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems for managing power and energy expenditures in cores of a processor to balance performance with power and energy dissipation are disclosed. Embodiments may include pre-decoder(s) between levels of cache or between main memory and a level of cache to monitor core execution rates by associating power tokens with each instruction. The power tokens include values representing the average power dissipated by the core for instructions and a sum of the power tokens may be compared with a state of management control bits for performance, energy, and power, to determine whether to increase or decrease power dissipation in the core. The power dissipation is varied by, e.g., adjusting the issue rate of instructions, adjusting the execution rate of instructions, turning off unused units within the core, controlling the frequency and voltage of the core, and switching tasks between cores.

Claims

1. A method for pre-decoding instructions prior to storage of the instruction in a level one cache for a processor core, for managing power dissipation in the processor core, the method comprising:

re-encoding an opcode of an instruction to incorporate a power token, the power token comprising a bit to indicate a unit of the processor core to turn off during execution of the instruction; and

adjusting the power dissipation in the processor core based upon a state of management control bits associated with the power dissipation, in response to a dynamic power count for the processor core based upon issuance of the instruction.

2. The method of claim 1, further comprising adjusting the frequency of the processor core and the voltage of the processor core in response to the dynamic power count.

3. The method of claim 1, further comprising adjusting the power dissipation in the processor core based upon a threshold associated with the dynamic power count, the threshold being related to a physical limitation of the processor core.

4. The method of claim 1, further comprising modifying execution flags associated with the instruction, the execution flags to schedule issuance of the instruction with respect to other instructions in a parallel execution group that comprises the instruction.

5. The method of claim 1, wherein re-encoding the opcode comprises selecting the power token from a look-up table, wherein the look-up table comprises the power token and other power tokens for instructions to be executed by the processor core.

6. The method of claim 1, wherein re-encoding the opcode comprises selecting the a new opcode that identifies the instruction and power dissipation associated with the instruction.

7. The method of claim 6, wherein the opcode and the new opcode utilize an equal number of bits.

9. The method of claim 6, wherein pre-decoding comprises:

generating a power token for an instruction of the instructions, wherein the power token is associated with a relative average power that the instruction consumes during execution; and

re-encoding an opcode of the instruction to include the power token.

10. The method of claim 9, wherein re-encoding an opcode comprises ranking the instructions based upon power dissipated by each of the instructions and encoding the opcode based upon the ranking.

11. The method of claim 9, wherein monitoring comprises selecting valid completions associated with the instructions.

12. The method of claim 11, wherein creating the dynamic power count comprises summing the power token with other power tokens associated with the valid completions and adding the sum of the power tokens to a total dynamic weighted execution rate.

13. The method of claim 12, wherein creating the dynamic power count comprises periodically loading the total dynamic weighted execution rate into a buffer.

8. A method, comprising:

monitoring an instruction execution rate for a processor core;

creating a dynamic power count representative of power dissipation in the processor core based upon the instruction execution rate; and

pre-decoding instructions prior to storage in a level one cache to dynamically adjust power dissipation by the processor core based upon the dynamic power count.

14. The method of claim 8, wherein pre-decoding comprises identifying a set of the instructions, each instruction of the set having a result that is independent of the results of other instructions in the set.

15. The method of claim 8, wherein pre-decoding comprises delineating a group of the instructions for parallel execution based upon stop bit execution flags associated with the instructions.

16. The method of claim 15, wherein pre-decoding comprises selecting instructions from the group to modify the dynamic power count, based upon a state of management control bits, to determine a parallel instruction issue schedule.

17. The method of claim 16, wherein selecting instructions from the group comprises adjusting execution flags associated with the instructions to decrease the dynamic power count.

18. The method of claim 8, wherein pre-decoding comprises incorporating a bit in a power token associated with the instructions to control clock degating of units in the processor core, wherein the units comprise dynamic logic.

19. The method of claim 8, wherein pre-decoding comprises incorporating a bit in a power token associated with the instructions to maintain inputs for units in the processor core, wherein the units comprise static logic.

20. The method of claim 8, wherein pre-decoding comprises modifying the frequency and voltage associated with the processor core based upon the dynamic power count.

21. A method, comprising:

encoding instructions with a power token between levels of cache for a processor core, to monitor power dissipation in the processor core;

determining a dynamic weighted execution rate based upon the power tokens that are associated with instructions executed by the processor core; and

adjusting power dissipation by the processor core based upon the dynamic weighted execution rate.

22. The method of claim 21, wherein encoding comprises selecting a power token for the instructions from a table of power tokens, wherein the table comprises a pre-determined power token for each of the instructions.

23. The method of claim 21, wherein determining the dynamic weighted execution rate comprises summing the power tokens upon execution of the instructions and adding the sum to the dynamic weighted execution rate.

24. The method of claim 21, wherein adjusting the power dissipation comprises modifying execution flags to adjust an issue rate associated with the instructions.

25. The method of claim 21, wherein adjusting the power dissipation comprises adjusting the frequency and voltage of the processor core.

26. The method of claim 21, wherein adjusting the power dissipation comprises adjusting a number of the instructions associated with a group to execute in parallel via the processor core.

27. The method of claim 21, wherein adjusting the power dissipation comprises transmitting a signal to an operating system to switch tasks associated with the processor core.

28. A method for encoding opcodes of instructions, the method comprising:

ranking the instructions in accordance with a criteria; and

assigning opcodes to the instructions based upon the ranking, wherein each opcode identifies an instruction of the instructions and indicates a relative ranking of the instruction according to the criteria, with respect to the instructions.

29. The method of claim 28, wherein the opcodes comprise weighted values associated with the criteria.

30. The method of claim 29, wherein each of the weighted values represents an average power dissipation for an associated instruction of the instructions.

31. A pre-decoder residing between levels of cache for managing power dissipation in a processor core, the pre-decoder comprising:

a re-encoder to re-encode an opcode of an instruction to incorporate a power token, the power token comprising a bit to indicate a unit of the processor core to turn off during execution of the instruction; and

transform control logic to adjust the power dissipation in the processor core based upon management control bits associated with the power dissipation, in response to a dynamic power count for the processor core.

32. The pre-decoder of claim 31, further comprising a frequency index coupled with the transform control logic to control the frequency of the processor core and a voltage index coupled with the transform control logic to control the voltage of the processor core.

33. The pre-decoder of claim 31, further comprising a threshold buffer having a representation of a physical limitation of the processor core, the physical limitation being related to the dynamic power count, wherein the threshold buffer is coupled with the transform control logic to adjust the power dissipation in the processor core.

34. The pre-decoder of claim 31, further comprising an execution flag register coupled with the transform control logic to modify execution flags associated with the instruction, the execution flags to schedule issuance of the instruction with respect to other instructions in a parallel execution group associated with the instruction.

35. The pre-decoder of claim 31, wherein the re-encoder comprises a power token table, the power token table having the power token and power tokens for other instructions to be executed by the processor core.

36. The pre-decoder of claim 31, wherein the re-encoder is configured to select a new opcode that identifies the instruction and power dissipation associated with the instruction.

37. The pre-decoder of claim 36, wherein the opcode and the new opcode utilize an equal number of bits.

38. A pre-decoder residing between levels of cache for re-encoding opcodes of instructions, the pre-decoder comprising:

a table having new opcodes for the instructions, wherein each opcode is associated with one of the instructions and indicates a relative ranking of the instructions according to a criteria; and

a re-encoder to match an instruction with a new opcode of the new opcodes in the table based upon an association between the new opcode and the instruction, to replace an opcode of the instruction with the new opcode in response to receiving the instruction.

39. The pre-decoder of claim 38, wherein the opcodes comprise weighted values associated with the criteria.

40. The pre-decoder of claim 39, wherein each of the weighted values represents an average power dissipation for an associated instruction of the instructions.

41. A system, comprising:

a summer to sum power tokens associated with instructions executed by a processor core;

an adder coupled with the summer to generate a dynamic weighted execution rate representative of power dissipation in the processor core based upon the sum;

a register to maintain a dynamic power count based upon the dynamic execution rate; and

a pre-decoder coupled with the register, residing between main memory and a level one cache for the processor core, to associate the power tokens with the instructions and to dynamically adjust power dissipation by the processor core based upon the dynamic power count and a state of management control bits.

42. The system of claim 41, wherein the pre-decoder comprises a re-encoder to incorporate the power tokens into opcodes associated with the instructions, wherein each power token indicates a relative average power that the associated instruction of the instructions is to consume during execution by the processor core.

43. The system of claim 42, wherein the power tokens comprise bits to control clock degating of units in the processor core, wherein the units comprise dynamic logic.

44. The system of claim 42, wherein the power tokens comprise bits to prevent inputs for units in the processor core from changing, wherein the units comprise static logic.

45. The system of claim 41, wherein the pre-decoder comprises a base pre-decoder to identify a set of the instructions, each instruction of the set having a result that is independent of the results of other instructions in the set.

46. The system of claim 41, wherein pre-decoding comprises a base pre-decoder to delineate a group of the instructions for parallel execution based upon stop bit execution flags associated with the instructions.

47. The system of claim 46, wherein pre-decoding comprises a base pre-decoder to select instructions from the group to modify the dynamic power count, based upon the state of management control bits, to determine a parallel instruction issue schedule.

48. The system of claim 46, wherein the base pre-decoder is configured to adjust the execution flags to decrease the dynamic power count.

49. The system of claim 41, wherein the pre-decoder is configured to modify a frequency and voltage associated with the processor core.