Mixed hardware/sofware architecture and method for processing xDSL communications

• US 20050071800A1
• Filed: 11/10/2004
• Published: 03/31/2005
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Granted Patent: US 8,325,751 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of a particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs achievable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field. A system constructed in this fashion is highly gate efficient and cost effective, so that a multiport system can be put on single SOC integrated circuit.

Claims

1. A communication system comprising:

a common memory for storing data;

at least one communication port to receive a data transmission;

a first hardware subsystem to perform a first operation associated with the received data transmission and to store data related to the first operation in the common memory; and

a software subsystem to perform a second operation associated with the received data transmission and to store data related to the second operation in the common memory, and

wherein the first hardware subsystem and the software subsystem are capable of accessing data stored in the common memory to perform the first and second operations, respectively.

2. The communication system of claim 1, wherein the first hardware system accesses data stored in the common memory related to an operation performed by the software subsystem.

3. The communication system of claim 1, wherein the software subsystem accesses data stored in the common memory related to an operation performed by the first hardware subsystem.

4. The communication system of claim 1 further comprising:

a second hardware subsystem to perform a third operation associated with the received data transmission and to store data related to the third operation in the common memory, wherein the second hardware subsystem is capable of accessing data stored in the common memory to perform the third operation.

5. The communication system of claim 4, wherein the second hardware system accesses data stored in the common memory related to an operation performed by the software subsystem.

6. The communication system of claim 4, wherein the first and second hardware subsystems include application specific integrated circuit (ASIC) modules to perform the first and third operations, respectively, and wherein the software subsystem includes a digital signal processor (DSP) to perform the second operation by executing program instructions.

7. The communication system of claim 6, wherein first and third operations are physical medium dependent (PMD) and transport convergence (TC) operations, respectively.

8. The communication system of claim 7, wherein the second operation is not a PMD operation or a TC operation.

9. In a communication system having a first pipeline stage and a second pipeline stage coupled to a common memory, a communication method comprising:

receiving a data transmission;

performing a first operation associated with the received data transmission and storing data related to the first operation in the common memory by the first pipeline stage;

performing a second operation associated with the received data transmission and storing data related to the second operation in the common memory by the second pipeline stage;

accessing data stored in the common memory related to the second operation and performing a third operation by the first pipeline stage; and

accessing data stored in the common memory related to the first operation and performing a fourth operation by the second pipeline stage.

10. The method of claim 9, wherein the first pipeline state includes hardware modules and the second pipeline stage includes software modules.

11. The method of claim 9, wherein performing the first and second operations include performing a physical medium dependent (PMD) operation or a transport convergence (TC) operation.

12. The method of claim 11, wherein performing the second or fourth operations include performing a non-PMD operation or a non-TC operation.

13. A communication system comprising:

at least one communication port to receive data to be processed via a plurality of operation stages;

a hardware subsystem to perform a hardware operation associated with the received data;

a software subsystem to perform a software operation associated with the received data; and

an operation determining logic to determine as least one of the operation stages to be performed by at least one of the hardware subsystem and the software subsystem.

14. The system of claim 13, wherein the operation determining logic that determines the operation stage to be performed by at least one of the hardware subsystem and the software subsystem based on a first, a second, and a third number of instructions per second (MIPs) required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

15. The system of claim 13, wherein the operation determining logic determines the operation stage to be performed by at least one of the hardware subsystem and the software subsystem based on a first, a second, and a third number of gates and/or transistors required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

16. The system of claim 13, wherein the operation determining logic determines the operation stage to be performed by at least one of the hardware subsystem and the software subsystem based on a first, a second, and a third number of MIPs per gates and/or transistors required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

17. The system of claim 13, wherein the operation determining logic determines the operation stage to be performed by at least one of the hardware subsystem and the software subsystem based on a first, a second, and a third number of instructions required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

18. The system of claim 13, wherein the operation determining logic determines the operation stage to be performed by at least one of the hardware subsystem and the software subsystem based on a first, a second, and a third amount of power consumption required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

19. The system of claim 13, wherein the operation determining logic determines the operation stage to be performed by at least one of the hardware subsystem and the software subsystem based on a first, a second, and a third time period required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

20. The system of claim 13, wherein the system further includes a memory for storing the data, wherein the hardware subsystem and the software subsystem are capable of accessing the data stored in the memory and stored the processed data into the memory.

21. The system of claim 20, wherein the memory includes a first page to output the data and a second page to input the data.

22. The system of claim 13, wherein the operation stages are performed in an order.

23. The system of claim 22, wherein the order is flexible and alterable.

24. The system of claim 13, wherein the hardware subsystem may perform the hardware operation while the software subsystem performs the software operation.

25. The system of claim 13, wherein the data includes at least one of a bit stream, a packet based stream, and a cell based stream.

26. The system of claim 13, wherein at least one of the hardware operation is a physical medium dependent operation or a convergence operation and at least one of the software operation is a physical medium dependent operation or a convergence operation.

27. The system of claim 13, wherein that data further includes a data signal and a control information.

28. The system of claim 27, wherein the control information further includes at least one of an information identifying the communication port associated with the data,m a communication path associated with the data including whether the data is associated with a transmit operation or a receive operation, and an operation and/or port specific information such that at least one of the monitoring, testing, and adaptive feedback can be generated by a first operation stage to a second operation stage.

29. The system of claim 13, wherein the communication system further includes a plurality of ports having a plurality of clock rate respectively.

30. The system of claim 29, wherein the communication system further includes an internal clock device for generating an internal clock, wherein the rate of the internal clock is faster than the rate of each of the clocks associated with the ports respectively.

31. The system of claim 30, wherein the internal clock is programmable and adjustable.

32. A communication method comprising:

receiving a data to be processed via a plurality of operation stages;

determining at least one of the operatin stages to be performed by at least one of a hardware subsystem and a software subsystem; and

performing the operation stage on the data based on the determined result.

33. The method of claim 32, wherein the step of determining determines at least one of the operation stages based on a first, a second, and a third number of instructions per second (MIPs) required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

34. The method of claim 32, wherein the step of determining determines at least one of the operation stages based on a first, a second, and a third number of gates and/or transistors required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

35. The method of claim 32, wherein the step of determining determines at least one of the operation stages based on a first, a second, and a third number of MIPs per gates and/or transistors required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

36. The method of claim 32, wherein the step of determining determines at least one of the operation stages based on a first, a second, and a third number of instructions required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

37. The method of claim 32, wherein the step of determining determines at least one of the operation stages based on a first, a second, and a third amount of power consumption required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

38. The method of claim 32, wherein the step of determining determines at least one of the operation stages based on a first, a second, and a third time period required by the hardware subsystem, the software subsystem, and the combination of the hardware subsystem and the software system respectively to perform the operation stage.

39. The method of claim 32, wherein the operation stages are performed in an order.

40. The method of claim 39, wherein the order is flexible and alterable.

41. The method of claim 32, wherein the operation stages includes a first operation stage which to be performed by the hardware subsystem and a second operation stage which to be performed by the software subsystem, wherein the first operation stage and the second operation stage can be performed simultaneously.

42. The method of claim 32, wherein the data can be at least one of a bit stream, a packet based stream, and a cell based stream.

43. The method of claim 32, wherein at least one of the operation stages is a physical medium dependent operation or a convergence operation.

44. The method of claim 32, wherein that data further includes a data signal and a control information.

45. The method of claim 44, wherein the control information further includes at least one of an information identifying the communication port associated with the data, a communication path associated with the data including whether the data is associated with a transmit operation or a receive operation, and an operation and/or port specific information such that at least one of the monitoring, testing, and adaptive feedback can be generated by a first operation stage to a second operation stage.