Semiconductor device and manufacturing method thereof

• US 20050073004A1
• Filed: 08/31/2004
• Published: 04/07/2005
• Est. Priority Date: 09/25/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Miyahara, Shouji, Ishida, Hiroyasu, Onda, Masahito, Kubo, Hirotoshi
• Granted Patent: US 7,230,300 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Claims

1. A semiconductor device, comprising:

an element region which is provided by diffusing prescribed impurities on a semiconductor substrate;

a surrounding region which is surrounding an outer periphery of the element region;

a trench which is provided on the semiconductor substrate in the surrounding region;

an insulating film which is formed in the trench; and

a conductive material which is buried in the trench, wherein an electric potential which is applied to the substrate is also applied to the conductive material.

3. The semiconductor device according to claim 1 or 2, wherein the conductive material is polysilicon.

4. The semiconductor device according to claim 1 or 2, wherein a high concentration impurity region, which is in contact with the conductive material, is provided on a surface of the substrate in the surrounding region.

2. A semiconductor device, comprising:

an element region in which an insulating gate semiconductor element of a trench type is provided on a semiconductor substrate;

a surrounding region which is surrounding an outer periphery of the element region;

a trench which is provided on the semiconductor substrate in the surrounding region;

an insulating film which is formed in the trench; and

a conductive material which is buried in the trench, wherein an electric potential which is applied to the substrate is also applied to the conductive material.

5. A method of manufacturing a semiconductor device, which includes an element region where a prescribed element is formed and a surrounding region which is surrounding an outer periphery of the element region, comprising:

a step of forming a trench in the surrounding region;

a step of forming an insulating film on inner walls of the trench;

a step of burying a conductive material in the trench; and

a step of electrically connecting the conductive material which has been buried in the trench and a substrate.

7. The method of manufacturing the semiconductor device according to claim 5 or 6, wherein a high concentration impurity region is formed on a surface of the semiconductor substrate in the surrounding region in a step of forming the element region.

8. The method of manufacturing the semiconductor device according to claim 7, wherein the high concentration impurity region is formed by an ion implantation process.

6. A method of manufacturing a semiconductor device, which includes an element region where an element of a trench type is formed on a semiconductor substrate and a surrounding region which is surrounding an outer periphery of the element region, comprising:

a step of forming a first trench in the surrounding region, and forming a second trench in the element region;

a step of forming insulating films on inner walls of the first trench and the second trench;

a step of burying conductive materials in the first trench and the second trench;

a step of forming an element region by diffusing prescribed impurities in a periphery of the second trench; and

a step of electrically connecting the conductive material which has been buried in the first trench and the semiconductor substrate, and forming a prescribed electrode which is in contact with the element region.