ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH

• US 20050073023A1
• Filed: 10/06/2003
• Published: 04/07/2005
• Est. Priority Date: 10/06/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Abadeer, Wagdi W., Fifield, John A., Tonti, William R.
• Granted Patent: US 6,879,021 B1
• Time in Patent Office: Days
• US Class Current: 257/530
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

Claims

1. An antifuse device operable at a voltage thereacross, comprising:

(a) a first element having a first conductive region, a second conductive region and a tunneling region located between said first and second conductive regions, said tunneling region operatively configured so that a tunneling current is present between said first and second conductive regions of said first element when the voltage is applied across the antifuse device;

(b) a second element having a first conductive region, a second conductive region and a tunneling region located between said first and second conductive regions, said tunneling region operatively configured so that a tunneling current is present between said first and second conductive regions of said second element when the voltage is applied across the antifuse device; and

(c) an output node electrically coupled between said first element and said second element.

2. An antifuse device according to claim 1, wherein the antifuse device has a programming state and further comprises a sensing circuit electrically coupled to said output node, said sensing circuit operatively configured for sensing the programming state and outputting the programming state as a logic-level signal.

3. An antifuse device according to claim 2, wherein said sensing circuit is a latchless sensing circuit.

4. An antifuse device according to claim 1, wherein said sensing circuit consists essentially of an inverter.

5. An antifuse device according to claim 1, wherein the antifuse device has an unprogrammed state and a programmed state aid said output node has a corresponding unprogrammed voltage and programmed voltage when the voltage is applied across the antifuse device, the difference between said unprogrammed voltage and said programmed voltage being at least 400 mV when the voltage is 1 volt.

6. An antifuse device according to claim 5, wherein the difference between said unprogrammed voltage and said programmed voltage being at least 700 mV when the voltage is 1 volt.

7. An antifuse device according to claim 1, wherein said second element has an unprogrammed state and a programmed state, wherein in said unprogrammed state said tunneling region of said second element is essentially non-conducting when the voltage is applied across the antifuse device and in said programmed state said tunneling region of said second element is conducting when the voltage is applied across the antifuse device.

8. An antifuse device according to claim 7, further comprising a programming circuit operatively configured for changing said unprogrammed state to said programmed state.

9. An antifuse device according to claim 8, further comprising an isolation element located between said first and second elements, said isolation element operatively configured to isolate said first element from said second element while said programming circuit is programming said second element.

10. An antifuse device according to claim 1, wherein said tunneling region of said second element comprises a thin oxide layer.

11. An antifuse device according to claim 10, wherein said tunneling region of said first clement comprises a thin oxide layer.

12. An antifuse device according to claim 11, wherein said thin oxide layer has an equivalent electrical thickness of no more than about 19 Å

.

13. An antifuse device according to claim 1, wherein each of said first and second elements is made from a semiconductor capacitor.

14. An antifuse device according to claim 1, wherein each of said first and second elements is made from a semiconductor transistor.

15-20. -20. (canceled)

21. A programmable antifuse device, comprising:

(a) a first element having a first conductive region, a second conductive region and a tunneling region located between said first and second conductive regions, said tunneling region operatively configured so that a tunneling current is present between said first and second conductive regions of said first element when the voltage is applied across the antifuse device;

(b) a second element having a first conductive region, a second conductive region and a tunneling region located between said first and second conductive regions, said tunneling region operatively configured so that a tunneling current is present between said first and second conductive regions of said second element when the voltage is applied across the antifuse device; and

(c) a programming circuit in electrical communication with said second element and operatively configured to cause said tunneling region of said second element to become conductive when said programming circuit is energized.

22. An antifuse device according to claim 21, wherein each one of said bias and antifuse elements is a thin-oxide device.

23. An antifuse device according to claim 21, further comprising a sensing circuit, electrically coupled between said first and second elements, operatively configured to sense the conductive state of said second element.

24. An antifuse device according to claim 23, wherein said sensing circuit is a latchless circuit.

25. An antifuse device according to claim 23, wherein said sensing circuit consists essentially of an inverter.

26. An antifuse device according to claim 21, further comprising an output node electrically coupled between said first and second elements and wherein the antifuse device has an unprogrammed state and a programmed state and said output node has a corresponding unprogrammed voltage and programmed voltage when the voltage is applied across the antifuse device, the difference between said unprogrammed voltage and said programmed voltage being at least 500 mV when a voltage of 1 volt is applied across said first and second elements.

29. An antifuse device according to claim 23, wherein said sensing circuit is a latchless circuit.

30. An antifuse device according to claim 23, comprising a plurality of antifuse devices comprising a corresponding plurality of second elements comprising a corresponding plurality of tunneling regions, said programming circuit in electrical communication with said plurality of antifuse devices and configured to cause said plurality of tunneling regions to become conductive substantially simultaneously with one another when said programming circuit is energized.

27. An integrated circuit chip, comprising:

(a) functional circuitry;

(b) at least one antifuse device operatively connected to said functional circuitry, said at least one antifuse device comprising;

(i) a first element having a first conductive region, a second conductive region and a tunneling region located between said first and second conductive regions, said tunneling region operatively configured so that a tunneling current is present between said first and second conductive regions of said first element when the voltage is applied across the antifuse device;

(ii) a second element having a first conductive region, a second conductive region and a tunneling region located between said first and second conductive regions, said tunneling region operatively configured so that a tunneling current is present between said first and second conductive regions of said second element when the voltage is applied across the antifuse device; and

(iii) an output node electrically coupled between said first element and said second element; and

(c) a programming circuit in electrical communication with said second element and operatively configured to cause said tunneling region of said second element to become conductive when said programming circuit is energized.

28. An integrated circuit chip according to claim 27, further comprising a sensing circuit, electrically coupled between said first and second elements, operatively configured to sense the conductive state of said second element.