Semiconductor integrated circuit device and manufacturing method thereof

• US 20050073051A1
• Filed: 06/21/2004
• Published: 04/07/2005
• Est. Priority Date: 09/24/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamamoto, Naoki, Mine, Toshiyuki, Nishida, Akio, Chakihara, Hiraku, Fujimoto, Akira, Matsuoka, Hideyuki
• Granted Patent: US 7,221,056 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A manufacturing process for a semiconductor integrated circuit device which prevents occurrence of reaction between metal wiring and a boron-doped silicon plug over it in heat treatment for a MOS transistor to be formed over them and reduces the possibility of rise in contact resistance. Metal boride is formed on an exposed metal surface in the bottom of an opening made in an interlayer insulating film over the metal wiring. In order to facilitate formation of such metal boride, metal oxide remaining on the metal surface is removed with an aqueous ammonia solution. The meal surface is irradiated with high energy ultraviolet light in order to remove organic matter remaining in the opening and facilitate removal of the metal oxide with the aqueous ammonia solution.

Claims

1. A semiconductor integrated circuit device comprising:

wiring of a first metal which is formed on a semiconductor substrate;

silicon-containing insulating film formed on the first metal wiring;

an opening which is made by removing a given area of the insulating film and boring it until the first metal wiring is reached; and

a plug of silicon doped with N-type or P-type impurities, buried in the opening,

wherein a metal compound containing the first metal and boron is formed on the surface of the first metal present in the bottom of the opening.

3. The semiconductor integrated circuit device according to claim 1, wherein the metal compound contains a metal element as an ingredient of the first meal wiring and silicon.

4. The semiconductor integrated circuit device according to claim 1,

wherein the plug consists of a silicon layer doped with N-type or P-type impurities, buried in the opening;

and

wherein the silicon layer remains inside the opening or inside the opening and on the insulating film surface around the opening.

5. The semiconductor integrated circuit device according to claim 1,

wherein the plug consists of a silicon layer doped with N-type or P-type impurities, buried in the opening;

and

wherein one end of the plug is in touch with a metal compound of the first metal and boron, formed on the surface of the first metal present in the bottom of the opening, and at its other end, the silicon layer remains inside the opening or inside the opening and on the insulating film surface around the opening.

6. The semiconductor integrated circuit device according to claim 1, wherein a silicon layer doped with N-type or P-type impurities which is formed on the insulating film with one end of it connected with the plug is used as a source or drain of a MOS transistor.

7. The semiconductor integrated circuit device according to claim 1, having a vertically multi-layered MOS transistor on the semiconductor substrate,

wherein a first silicon layer doped with N-type or P-type impurities of a first concentration which is formed on the insulating film with one end of it connected with the plug is used as a source or drain of a MOS transistor,

wherein a second silicon layer is laid over the first silicon layer and used as a channel region, the second silicon layer containing virtually no such impurities as contained in the first silicon layer or containing impurities of the type opposite to the type of the impurities contained in the first silicon layer as effective impurities, and

wherein a third silicon layer doped with N-type or P-type impurities of the first concentration is laid over the second silicon layer and used as a drain or source.

8. The semiconductor integrated circuit device according to claim 1, having a MOS transistor,

wherein a first silicon layer doped with N-type or P-type impurities of a first concentration which lies on the insulating film with one end of it connected with the plug, parallel to the semiconductor substrate, is used as a source or drain of a MOS transistor,

wherein a second silicon layer adjacent to the first silicon layer is used as a channel, the second silicon layer containing virtually no such impurities as contained in the first silicon layer or containing impurities of the type opposite to the type of the impurities contained in the first silicon layer as effective impurities, and

wherein a third silicon layer adjacent to the second silicon layer and doped with N-type or P-type impurities of the first concentration is used as a drain or source.

9. The semiconductor integrated circuit device according to claim 1, wherein the P-type impurities are boron.

10. The semiconductor integrated circuit device according to claim 1, wherein the N-type impurities are phosphorus or arsenic.

2. A semiconductor integrated circuit device comprising:

wiring of a first metal which is formed on a semiconductor substrate; and

a plug of silicon doped with N-type or P-type impurities, formed on a given area of the first metal wiring,

wherein a metal compound containing the first metal and boron is formed on the surface of the first metal.

11. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

making wiring of a first metal on a semiconductor substrate;

forming a silicon-containing insulating film on the first metal wiring;

making an opening by removing a given area of the insulating film and boring it until the first metal wiring is reached;

forming a metal compound of the first metal and boron by implanting boron into the surface of the first metal present in the bottom of the opening; and

depositing silicon doped with N-type or P-type impurities on the opening.

12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein in the metal compound forming step, a compound of the first metal and boron is formed on the surface of the first metal through a self-align process by irradiation with boron hydride gas.

13. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein in the metal compound forming step, a compound of the first metal, boron, and silicon is formed on the surface of the first metal through a self-align process by irradiation with boron hydride gas and silicon hydride or silicon chloride gas.

14. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein a compound of the first metal and boron is formed on the surface of the first metal present in the bottom of the opening through a self-align process by irradiating the opening with compound gas as described in claim 12 or mixed gas as described in claim 13 and then a plug of silicon doped with N-type or P-type impurities, buried in the opening, is formed.

15. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein a compound of the first metal and boron is formed on the surface of the first metal by implanting boron ions in the surface of the first metal present in the bottom of the opening using a given accelerating voltage and then a plug of silicon doped with N-type or P-type impurities, buried in the opening, is formed.

16. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein a compound of the first metal and boron is formed on the surface of the first metal by forming a very thin silicon layer on the surface of the first metal present in the bottom of the opening and implanting boron ions using a given accelerating voltage in a way to reach the silicon layer and the first metal surface, and then a plug of silicon doped with N-type or P-type impurities, buried in the opening, is formed.

17. The method of manufacturing a semiconductor integrated circuit device according to claim 11, comprising the steps of:

implanting boron ions in the surface of the first metal present in the bottom of the opening using a given accelerating voltage;

forming a compound of the first metal, boron, and silicon on the surface of the first metal through heat treatment; and

forming a plug of silicon doped with N-type or P-type impurities, buried in the opening.

18. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein at the metal compound forming step, the surface of the first metal present in the bottom of the opening is immersed in an aqueous ammonia solution and then the metal compound is formed.

19. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the surface of the first metal present in the bottom of the opening is immersed in an aqueous ammonia solution and then a compound of the first metal and boron is formed on the surface of the first metal.

20. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein a compound of the first metal and boron is formed on the surface of the first metal present in the opening and the surface of the first metal is immersed in an aqueous ammonia solution and then a plug of silicon doped with N-type or P-type impurities, buried in the opening, is formed.

21. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the surface of the first metal present in the bottom of the opening is irradiated with ultraviolet light to remove organic matter from the surface of the first metal.

22. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the surface of the first metal present in the bottom of the opening is irradiated with ultraviolet light to oxidize the surface of the first metal.

23. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the surface of the first metal present in the bottom of the opening is irradiated with both first ultraviolet light with a first wavelength and second ultraviolet light with a second wavelength.

24. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the surface of the first metal present in the bottom of the opening is irradiated with both first ultraviolet light with a selected wavelength in the range from 140 nm to 180 nm and second ultraviolet light with a selected wavelength in the range from 210 nm to 260 nm to remove organic matter from the first metal surface and form a metal oxide film on the first metal surface and is immersed in an aqueous ammonia solution to let the metal oxide film be dissolve in the aqueous ammonia solution, and then a metal compound of the first metal and boron is formed.