Capacitance detector circuit, capacitance detection method, and fingerprint sensor using the same

• US 20050073324A1
• Filed: 09/14/2004
• Published: 04/07/2005
• Est. Priority Date: 10/02/2003
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Inventors: Sato, Junichi, Umeda, Yuichi
• Granted Patent: US 7,075,316 B2
• Time in Patent Office: Days
• US Class Current: 324/662
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

A capacitance detecting circuit of a capacitive sensor having a plurality of column lines and a row line intersecting the column lines detects a change in capacitance at an intersection of a column line and a row line. The circuit includes a PN code generating unit for generating a code having orthogonality in time sequence to output the generated code as a column drive signal, a column line drive unit for driving a predetermined one of the column lines which are selected in response to the code, a capacitance detecting unit, connected to the row line, for detecting a voltage by converting a total sum of changes in capacitance at intersections of the selected column lines into the voltage to output the detected voltage, and a decode processing unit for performing a predetermined calculation on the detected voltage output from the capacitance detecting unit and the code to determine a voltage value responsive to the capacitance change at the intersection.

Claims

1. A circuit of a capacitive sensor having a plurality of column lines and a row line intersecting the column lines, for detecting a change in capacitance at an intersection of a column line and a row line, the circuit comprising:

code generating means for generating a code having orthogonality in time sequence to output the generated code as a column drive signal;

column line drive means for driving a plurality of column lines, from among the column lines that are selected in response to the code;

capacitance detecting means, connected to the row line, for detecting a voltage by converting a total sum of changes in capacitance at intersections of the selected column lines into the voltage to output the detected voltage; and

decode processing means for performing a predetermined calculation on the detected voltage output from the capacitance detecting means and the code to determine a voltage value responsive to the capacitance change at the intersection.

2. A circuit according to claim 1, wherein the code generating means generates a PN code, and outputs the PN code with the phase thereof varied in time sequence.

3. A circuit according to claim 2, wherein the code generating means outputs the PN code with the phase thereof shifted bit by bit in time sequence.

4. A circuit according to claim 2, wherein the code generating means outputs the PN code with the phase thereof shifted by a random number of bits in time sequence.

5. A circuit according to claim 2, wherein the code generating means repeats by a plurality of times a cycle within which the phase of the PN code is varied by a number of bits equal to the number of bits of the PN code, and wherein the decode processing means determines a voltage responsive to a change in capacitance at the intersection on a per cycle basis, sums the voltage for a plurality of cycles, and outputs the summed result as the detected voltage.

6. A circuit according to claim 5, wherein the code generating means generates a plurality of PN codes, and switches the PN code from one PN code to a different PN code every cycle.

7. A circuit according to claim 2, wherein the PN code comprises an M sequence.

8. A circuit according to claim 1, wherein the code generating means generates a Walsh code having bit strings varying in time sequence, and outputs the Walsh code as the code thereof.

9. A circuit according to claim 1, wherein the decode processing means performs a decode process by multiplying and summing a data string of the detected voltage that is output in accordance with the code in time sequence.

10. A circuit according to claim 1, wherein a capacitance at an intersection is detected in an area type capacitive sensor which includes a matrix of intersections of a plurality of column lines and a plurality of row lines.

11. A circuit according to claim 1, wherein a capacitance at an intersection is detected in a line type capacitive sensor which includes a single row line and a plurality of column lines intersecting the row line.

12. A fingerprint sensor comprising a circuit according to claim 1.

13. A method for detecting a change in capacitance at an intersection of a column line and a row line in a capacitive sensor that includes a plurality of column lines and a plurality of row lines, the method comprising the steps of:

generating a code with the phase thereof varied in time sequence to output the code as a column drive signal;

driving a plurality of column lines, from among the column lines, selected in response to the code;

detecting a voltage by converting a total sum of changes in capacitance at intersections of the selected column lines into the voltage to output the voltage as a detected voltage; and

decoding a data string of the detected voltage output in the detecting step in accordance with the code in a predetermined calculation to determine a voltage value responsive to the capacitance change at the intersection.

14. A circuit for detecting a change in capacitance at an intersection of a column line and a row line in a capacitive sensor that includes a plurality of column lines and a row line intersecting the column lines, the circuit comprising:

code generating means for generating a code having orthogonality in time sequence;

column line group selecting means for dividing the plurality of column lines into groups, each group including a predetermine number of column lines, and for selecting a group of column lines to be measured;

column line drive means for driving the plurality of column lines in each of the successively selected column line groups in response to the code;

capacitance detecting means, connected to the row line, for converting a total sum of changes in capacitance at intersections of the selected column lines into a voltage signal, and outputting the voltage signal as a detected voltage; and

decode processing means for performing a predetermined calculation on the measured voltage and the code on a per column line group basis, and for determining a voltage value responsive to the capacitance change at each intersection.

15. A circuit according to claim 14, wherein the column line group comprises a predetermined number of adjacent column lines.

16. A circuit according to claim 14, wherein the column line group comprises column lines spaced at predetermined intervals.

17. A circuit according to claim 14, wherein the code generating means generates a PN code, and outputs the PN code with the phase thereof varied in time sequence.

18. A circuit according to claim 17, wherein the code generating means outputs the PN code with the phase thereof shifted bit by bit in time sequence.

19. A circuit according to claim 17, wherein the code generating means outputs the PN code with the phase thereof shifted by a random number of bits in time sequence.

20. A circuit according to claim 17, wherein the code generating means repeats by a plurality of times a cycle within which the phase of the PN code is varied by a number of bits equal to the number of bits of the PN code, and wherein the decode processing means determines a voltage responsive to a change in capacitance at the intersection on a per cycle basis, sums the voltage for a plurality of cycles, and outputs the summed result as the detected voltage.

21. A circuit according to claim 20, wherein the code generating means generates a plurality of PN codes, and switches the PN code from one PN code to a different PN code every cycle.

22. A circuit according to claim 17, wherein the PN code comprises an M sequence.

23. A circuit according to claim 17, wherein the code generating means generates a Walsh code having bit strings varying in time sequence, and outputs the Walsh code as the code thereof.

24. A fingerprint sensor comprising a capacitance detection circuit according to claim 14.

25. A method for detecting, as a voltage, a change in capacitance at an intersection of each of a plurality of column lines and a row line intersecting the column lines, the method comprising:

a code generating step for generating a code having orthogonality in time sequence;

a column line group selecting step for selecting a group of column lines to be measured, wherein the plurality of column lines are divided into the groups of column lines, each group including a predetermine number of column lines;

a column line drive step for driving the plurality of column lines in each of the successively selected column line groups in response to the code;

a capacitance measuring step for measuring capacitance by outputting, as a measured voltage, a total sum of currents responsive to capacitances at intersections of the row line and the plurality of driven column lines; and

a decode processing step for performing a predetermined calculation on the measured voltage and the code on a per column group basis and for determining a voltage value responsive to the capacitance at each intersection.