Differential amplifier and bit-line sense amplifier adopting the same

• US 20050073339A1
• Filed: 12/19/2003
• Published: 04/07/2005
• Est. Priority Date: 10/02/2003
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Rho, Kwang Myoung
• Application Number:
  US10/742,314
• Publication Number:
  US 20050073339A1
• Time in Patent Office: Days
• US Class Current: 327/50
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A bit-line sense amplifier is disclosed that includes switching elements to sequentially modify the sense amplifier to a negative feedback differential amplifier, a normal differential amplifier, a positive feedback differential amplifier, and a cross-coupled latch, in that order. The sense amplifier sensing data on a pair of bit-lines in a semiconductor memory; and a transistor is connected between one of the differential amplifiers and a common current source. The transistor has a resistance which is variable depending on a potential of an output of one of the differential amplifiers or remains constant by a different power source.

Claims

1. A differential amplifier, comprising:

a load connected between a voltage source, a first and a second output terminals;

a first transistor connected between the first output terminal and a first node, the third transistor being turned on depending on a first input signal;

a second transistor connected between the second output terminal and the first node, the second transistor being turned on depending on a second input signal;

a MOSFET resistor connected between the first node and a second node, the MOSFET resistor having a resistance which is variable depending on a potential of the first output terminal or the second output terminal; and

a common current source connected to the second node.

2. The differential amplifier according to claim 1, wherein the MOSFET resistor includes a PMOS transistor of which a gate is connected to the first output terminal or the second output terminal.

3. The differential amplifier according to claim 1, wherein the load comprises a first PMOS transistor connected between the voltage source and the first output terminal, and a second PMOS transistor connected between the voltage source and the second output terminal.

4. The differential amplifier according to claim 1, wherein the first and the second transistors are NMOS transistors.

5. The differential amplifier according to claim 1, wherein the load comprises a first NMOS transistor connected between the voltage source and the first output terminal, and a second NMOS transistor connected between the voltage source and the second output terminal.

6. The differential amplifier according to claim 1, wherein the first and the second transistors are PMOS transistors.

7. The differential amplifier according to claim 1, wherein the MOSFET resistor corresponds to an NMOS transistor of which a gate is connected to the first output terminal or the second output terminal.

8. A bit-line sense amplifier, comprising:

a plurality of switching elements to sequentially modify a sense amplifier to operate as a negative feedback differential amplifier, a normal differential amplifier, a positive feedback differential amplifier, and a cross-coupled latch, in that order, wherein the sense amplifier is adapted to sense data on a pair of bit-lines in a semiconductor memory; and

a transistor connected between the differential amplifier and a common current source, the transistor having a resistance which is variable depending on a potential of an output of one of the differential amplifiers or remains constant by a different power source.

9. The bit-line sense amplifier according to claim 8,

wherein the transistor is an NMOS transistor;

and

wherein the resistance is variable depending on an output of one of the differential amplifiers when the sense amplifier is operated as a differential amplifier, whereas the resistance remains constant when the sense amplifier is operated as a cross-coupled latch.

10. A bit-line sense amplifier, comprising:

a plurality of switching elements to sequentially modify a sense amplifier to operate as a negative feedback differential amplifier, a normal differential amplifier, and a cross-coupled latch depending on control signals, the sense amplifier adapting to sense data on a pair of bit-lines in a semiconductor memory;

a restore means for rewriting the sensed data on the pair of bit-lines and a selected cell in the semiconductor memory; and

a transistor connected between the differential amplifier and a common current source, the transistor having a resistance which is variable depending on a potential of an output of one of the differential amplifiers or remains constant by a different power source.

11. The bit-line sense amplifier according to claim 10,

wherein the transistor is an NMOS transistor;

and

wherein the resistance is variable depending on an output of one of the differential amplifiers when the sense amplifier is operated as the differential amplifier, whereas the resistance remains constant when the sense amplifier is operated as the cross-coupled latch.