Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter

• US 20050073452A1
• Filed: 09/22/2004
• Published: 04/07/2005
• Est. Priority Date: 04/18/2003
• Status: Active Grant

• Current Assignee: EDGEWATER WIRELESS SYSTEMS INC.
• Original Assignee: Engim, Inc.
• Inventors: Manganaro, Gabriele
• Granted Patent: US 7,324,034 B2
• Time in Patent Office: Days
• US Class Current: 341/150
• CPC Class Codes: H03M 1/0881 by forcing a gradual change from one output level to the next, e.g. soft-start
• CPC Class Codes: H03M 1/72 Sequential conversion in series-connected stages H03M1/68 takes precedence

Abstract

The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.

Claims

1. A switched-capacitor digital-to-analog converter comprising:

a plurality of cells, each cell comprising first and second switches switching respective voltages from a source to a charged capacitor; and

respective switch driver circuits each in electrical communication with a respective one of the first and second switches, each switch driver circuit applying a switch control signal to the switch, the switch control signals that turn the switch on differing to equalize the gate-to-source voltage difference.

2. The converter of claim 1, wherein the switch control signal comprises a gate voltage.

3. The converter of claim 1, wherein the first and second switches are transistor switches.

4. The converter of claim 3, wherein the transistor switches comprise a metal-oxide-semiconductor (MOS) device.

5. The converter of claim 1, wherein the respective switch driver circuits each comprise:

a first element receiving an external input, the first element providing an output responsive to the received input; and

a second element in electrical communication with the first element, the second element receiving the output and conditioning the output according to the difference between the respective voltages from the source.

6. The converter of claim 5, wherein the first element is a logic gate receiving one bit of a digital input word and a switching control signal.

7. The converter of claim 6, wherein the logic gate is a NAND gate.

8. The converter of claim 6, wherein the switching control signal is a clock signal.

9. The converter of claim 6, wherein the second element is a logic gate powered by a logic source level depending on the difference between the respective voltages from the source.

10. The converter of claim 9, wherein the logic source is an inverter.

11. The converter of claim 1, further comprising respective switches coupled between adjacent cells of the plurality of cells, the switches controllably connecting the cells ultimately producing an analog output corresponding to a digital input word.

12. The converter of claim 1, wherein the source comprises two emitter follower circuits and a resistor network, each coupled between electrical power and ground.

13. The converter of claim 12, wherein the emitter followers each comprises a bipolar junction transistor.

14. A method for data conversion using a switched-capacitor digital-to-analog converter comprising the steps of:

providing a plurality of cells, each cell comprising first and second switches switching respective different voltages from a source to a charged capacitor; and

providing respective switch driver circuits each in electrical communication with a respective one of the first and second switches; and

applying respective switch control signals to each of the first and second switches, the switch control signals that turn the switch on differing to equalize the gate-to-source voltage difference.

15. The method of claim 14, wherein applying the switch control signal comprises using a gate voltage.

16. The method of claim 14, wherein the first and second switches are transistor switches.

17. The method of claim 16, wherein the transistor switches comprise a metal-oxide-semiconductor (MOS) device.

18. The method of claim 14, further comprising:

receiving an external input, at a first element, the first element providing an output responsive to the received input; and

receiving at a second element in electrical communication with the first element, the second element, the output and conditioning the output according to the difference between the respective voltages from the source.

19. The method of claim 18, wherein the first element is a logic gate receiving one bit of a digital input word and a switching control signal.

20. The method of claim 19, wherein the logic gate is a NAND gate.

21. The method of claim 19, wherein the switching control signal is a clock signal.

22. The method of claim 19, wherein the second element is a logic gate powered by a logic source level depending on the difference between the respective voltages from the source.

23. The method of claim 22, wherein the logic source is an inverter.

24. The method of claim 14, further comprising providing respective switches coupled between adjacent cells of the plurality of cells, the switches controllably connecting the cells ultimately producing an analog output corresponding to a digital input word.

25. A switched-capacitor digital-to-analog converter comprising:

means for respectively switching different voltages from a source to a capacitor in each of a plurality of cells;

means for generating a switching control signal to respectively control the switching means in each of the plurality of cells; and

means for respectively differing the switching control signal to equalize the gate-to-source voltage.