Apparatus and method for disturb-free programming of passive element memory cells
First Claim
1. A method for programming a memory array of antifuse memory cells coupled between a respective array line on one memory array layer and a respective array line on another memory array layer, said memory cells comprising two opposite conductivity type semiconductor regions, one being more lightly-doped than the other, said method comprising:
- pulsing for a first time period a first selected array line coupled to the more heavily-doped region of a selected memory cell from an unselected bias voltage to a selected bias voltage; and
pulsing for a second time period a second selected array line coupled to the more lightly-doped region of the selected memory cell from an unselected bias voltage to a selected bias voltage;
wherein the first and second array line pulses are arranged so that the selected memory cell, once programmed, is reversed biased whenever the second selected array line is biased at an intermediate voltage closer to its unselected bias voltage than its selected bias voltage.
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Abstract
In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
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Citations
38 Claims
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1. A method for programming a memory array of antifuse memory cells coupled between a respective array line on one memory array layer and a respective array line on another memory array layer, said memory cells comprising two opposite conductivity type semiconductor regions, one being more lightly-doped than the other, said method comprising:
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pulsing for a first time period a first selected array line coupled to the more heavily-doped region of a selected memory cell from an unselected bias voltage to a selected bias voltage; and
pulsing for a second time period a second selected array line coupled to the more lightly-doped region of the selected memory cell from an unselected bias voltage to a selected bias voltage;
wherein the first and second array line pulses are arranged so that the selected memory cell, once programmed, is reversed biased whenever the second selected array line is biased at an intermediate voltage closer to its unselected bias voltage than its selected bias voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit comprising:
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a memory array of antifuse memory cells coupled between a respective array line on one memory array layer and a respective array line on another memory array layer, said memory cells comprising two opposite conductivity type semiconductor regions, one being more lightly-doped than the other; and
array support circuitry configured, when in a programming mode, for pulsing for a first time period a first selected array line coupled to the more heavily-doped region of a selected memory cell from an unselected bias voltage to a selected bias voltage, and for pulsing for a second time period a second selected array line coupled to the more lightly-doped region of the selected memory cell from an unselected bias voltage to a selected bias voltage, wherein the first and second array line pulses are arranged so that the selected memory cell, once programmed, is reversed biased whenever the second selected array line is biased at an intermediate voltage closer to its unselected bias voltage than its selected bias voltage. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification