Network-processor accelerator
First Claim
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1. A network apparatus comprising:
- a network interface for transmitting and receiving packets to and from a network;
a network processors for transferring the received packets to a next transfer destination;
a table memory for storing a table referred for the transfer of packets;
a cache memory for storing result of process of the network processor; and
a network-processor accelerator for transferring the received packets by referring to the cache memory;
wherein the network-processor accelerator transfers the received packets having the destination addresses which are identical to that of the received packets already processed with the network processor.
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Abstract
In order to perform cache processing for the received packets, a network apparatus is provided with a network-processor accelerator for caching the process result of a network processor. Accordingly, the network apparatus of the present invention ensuring higher packet-processing throughput can be realized by improving the packet-processing throughput without increase in the chip area, increase in the power consumption, and shortage in an external connected memory bandwidth.
34 Citations
26 Claims
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1. A network apparatus comprising:
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a network interface for transmitting and receiving packets to and from a network;
a network processors for transferring the received packets to a next transfer destination;
a table memory for storing a table referred for the transfer of packets;
a cache memory for storing result of process of the network processor; and
a network-processor accelerator for transferring the received packets by referring to the cache memory;
wherein the network-processor accelerator transfers the received packets having the destination addresses which are identical to that of the received packets already processed with the network processor. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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2. A network apparatus comprising:
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a network interface for transmitting or receiving packets to a network;
a first processor for transferring the received packets to a next transfer destination;
a table memory for storing a table referred for the transfer process;
a cache memory for storing result of process of the first processor; and
a second processor for transferring the received packets by referring to the cache memory;
wherein the received packets are transferred by referring to the result of process stored in the cache memory when the destination addresses thereof are identical to that of the packets processed and stored in the cache memory.
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17. A network-processor accelerator, comprising:
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an input interface unit for receiving packets;
a packet memory for temporarily storing the received packets;
a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets;
a cache memory for storing result of processes required for the transfer process of the received packets;
a means for determining whether the result of process to be applied to the received packets exists or not by referring to the cache memory; and
an output interface for transmitting the V packets. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A network processor including a means for caching the result of packet process, comprising:
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a primary table for management of packets when there is no relevant information in the cache; and
a secondary table for management of second and subsequent packets that are containing the relevant information not existing in the cache and are expected to provide the process result which is identical to that of the packets recorded in the primary table;
wherein the secondary tables are prepared in the number equal to the number of entries of the primary table for management of cache-miss packets and the number of entries of the respective secondary tables is all set to the constant value.
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24. A network processor including a means for caching the result of packet process, comprising:
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a primary table for management of packets when the relevant information does not exist in the cache; and
a secondary table for management of second and subsequent packets that are containing the relevant information not existing in the cache and are expected to provide the process result which is identical to that of the packets recorded in the primary table;
wherein the secondary table is placed under the management of a linked-list style.
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25. A network processor including a means for caching result of packet process, further comprising:
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a primary table for management of packets when there is no relevant information in the cache; and
a secondary table for management of the second and subsequent packets that are containing the relevant information not existing in the cache and are expected to provide the process result which is identical to that of the packets recorded in the primary table;
wherein the secondary table is placed under the management by utilizing the CAM or fully associative memory.
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26. A network-processor accelerator, comprising:
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an interface unit for temporarily storing the received packets;
a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets;
a cache memory for storing the process result required for transfer process of the received packets;
an address generation means for referring to the cache from the extracted information;
a means for determining whether the relevant information exists or not in the cache as the result of reference to the cache from the extracted information;
a means for reassembling the packets from the relevant information when the relevant information exists in the cache;
a primary table for management of the packets when the relevant information does not exist in the cache;
a secondary table for management of the second and subsequent packets that are containing the relevant information not existing in the cache and are expected to provide the process result which is identical to that of the packets recorded in the primary table;
an interface unit for transmitting the packets and necessary information to an external connected network processor for implementing, with a programmable manner, the processes of cache-miss packet recorded to the primary table;
an interface unit for receiving the processed packets and added information from the external connected network processor;
a means for recording the process result information of the processed packets to the cache;
a means for applying the process result to the relevant packets recorded to the secondary table;
a means for releasing the entries of the primary and secondary tables having completed the processes;
a means for generating the transmitting packets from the processed packets or the process result information; and
an interface unit for transmitting the processed packets.
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Specification