Semi-conductor wafer fabrication

• US 20050074907A1
• Filed: 10/06/2003
• Published: 04/07/2005
• Est. Priority Date: 10/06/2003
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kriz, Adrian, Monroe, Michael
• Application Number:
  US10/679,841
• Publication Number:
  US 20050074907A1
• Time in Patent Office: Days
• US Class Current: 438/9
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32

Abstract

A method of planarizing a semiconductor wafer includes applying a CMP process to a layer of dielectric material to planarize the wafer surface, and applying a plasma etching process to the wafer surface until a signal is generated from a detection layer that indicates that said detection layer has been removed from underlying features disposed on the water.

Claims

1. A method of fabricating a semiconductor wafer, comprising:

depositing a detection layer of material over a layer of feature material;

forming features in said feature material layer and said detection layer;

depositing a layer of dielectric over the wafer;

applying a CMP process to said wafer until said dielectric layer is planarized;

applying a plasma etching process to said wafer until said detection layer is removed to a level where said features are exposed; and

monitoring an optical signal during said plasma etching process, said optical signal being generated from the application of said plasma etching process to said detection aver.

2. The method of claim 1, wherein said CMP application step is stopped while a portion of said dielectric layer remains above said detection layer.

3. The method of claim 2, further comprising the step of adjusting said plasma etching process to achieve an approximately one to one ratio of etch rates of said dielectric layer and said detection layer.

4. The method of claim 2, wherein said remaining portion of said dielectric layer is at least 2000 Angstroms thick.

5. The method of claim 1, wherein said detection layer is completely removed by said plasma etching process.

6. The method of claim 1, further comprising the step of stopping said plasma etching process when said optical signal indicates that said detection layer has been removed from said feature material layer.

7. The method of claim 1, wherein said optical signal is a cyanide wavelength produced when said plasma etching process is applied to said detection layer.

8. The method of claim 1, wherein said detection layer is comprised of silicon nitride.

9. The method of claim 1, wherein said detection layer is comprised of a material that is harder than said feature material.

10. The method of claim 1, wherein said feature material is a conductive material.

11. A semiconductor wafer, comprising:

a plurality of features formed in a layer of feature material on a substrate, each of the features having an upper surface;

a layer of detection material capping each of said upper surfaces of said features; and

a layer of dielectric deposited onto said substrate and said detection layer.

12. The semiconductor wafer of claim 11, wherein said detection layer is comprised of a material that is harder than said feature material.

13. The semiconductor wafer of claim 11, wherein said detection layer is comprised of silicon nitride.

14. The semiconductor wafer of claim 11, wherein:

an optical signal having a first identifiable intensity level is generated when a plasma etching process is applied to said detection layer;

a second identifiable intensity level of said optical signal is generated when the plasma etching process is applied to said feature; and

said first identifiable intensity level is different than said second identifiable intensity level.

15. An integrated circuit, comprising:

a plurality of features separated by trenches, each said features having a top surface;

a layer of dielectric deposited in said trenches and substantially planar with said top surfaces of said feature, said planar nature of said dielectric layer and said top surfaces of said feature being achieved by a planarization process that includes plasma etching a layer of detection material capping said feature until it is determined that said detection layer has been removed from the feature.

16. The integrated circuit of claim 15, wherein said planarization process includes applying a CMP process to said dielectric layer before applying said plasma etching process.

17. The integrated circuit of claim 15, wherein said features are comprised of conductive material.

18. A method of planarizing a semiconductor wafer, comprising:

applying a CMP process to a layer of dielectric material at least until said dielectric layer is approximately planar; and

applying a plasma etching process to a detection layer of material until a signal is generated from said plasma etching process that indicates that said detection layer has been removed from underlying features.

19. The method of claim 18, wherein said signal is a change in an intensity level of a cyanide wavelength generated by said plasma etching process.

20. The method of claim 19, wherein said CMP process is stopped while a layer of dielectric remains covering said detection layer;

and wherein said plasma etching process begins while said dielectric layer remains covering said detection layer.

21. A method of removing dielectric material from a semiconductor wafer that has been previously planarized using a CMP process, comprising the step of applying a plasma etching process to a detection layer of material until an identifiable signal is generated from said plasma etching process that indicates that said detection layer has been substantially removed from underlying features disposed on the wafer.

22. The method of claim 21, wherein said signal is a change in an intensity level of a cyanide wavelength generated by said plasma etching process.

23. The method of claim 21, wherein said CMP process is stopped while a layer of dielectric remains covering said detection layer;

and wherein said plasma etching process begins while said dielectric layer remains covering said detection layer.