Method of manufacturing semiconductor device

• US 20050074941A1
• Filed: 01/22/2004
• Published: 04/07/2005
• Est. Priority Date: 10/02/2003
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Nagatomo, Hiroshi
• Granted Patent: US 7,078,287 B2
• Time in Patent Office: Days
• US Class Current: 438/301
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A gate electrode is formed on a silicon substrate. First spacers are formed on side surfaces of the gate electrode. With the gate electrode and the first spacers as masks, the surface of the silicon substrate is chipped off to form steplike portions at positions adjacent to base portions of the first spacers. Second spacers are formed at the steplike portions. Silicides are formed on the silicon substrate with the first spacers and the second spacers as masks.

Claims

1. A method of manufacturing a semiconductor device, comprising the following steps of:

forming a gate electrode on a silicon substrate;

forming first spacers on side surfaces of the gate electrode respectively;

chipping off the surface of the silicon substrate with the gate electrode and the first spacers as masks to thereby form steplike portions at positions adjacent to base portions of the first spacers;

forming second spacers at the steplike portions respectively; and

forming silicides on the silicon substrate with the first spacers and the second spacers as masks.

2. The method according to claim 1, wherein the steplike portions are respectively formed so as to have upward slanting surfaces.

3. The method according to claim 1, wherein the steplike portions are respectively formed so as to have surfaces vertical to the surface of the silicon substrate.

4. The method according to claim 1, wherein the steplike portions are respectively formed so as to have curved surfaces convex to the gate electrode.

5. The method according to claim 1, wherein the steplike portions are respectively formed so as to have downward slanting surfaces.

6. The method according to claim 1, wherein the formation of the silicides is done by depositing a metal on the surface of the silicon substrate by sputtering and effecting heat treatment thereon.

7. The method according to claim 6, wherein the metal is cobalt.

8. The method according to claim 1, wherein the gate electrode is formed of a polysilicon layer located on a gate oxide film, a tungsten layer located on the polysilicon layer and a silicon nitride film located on the tungsten layer.

9. The method according to claim 1, wherein a sidewall oxide film is formed on each side surface of the gate electrode and said each first spacer is formed thereon.

10. The method according to claim 1, wherein the second spacers are formed of an oxide film.

11. The method according to claim 10, wherein the formation of the second spacers is done by forming an oxide film for covering the surface of the silicon substrate, thereafter covering portions other than a device region, of the substrate surface with a resist pattern and anisotropically etching the oxide film in this condition.