Full match (FM) search algorithm implementation for a network processor
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Abstract
Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBS) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.
37 Citations
34 Claims
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1-23. -23. (canceled)
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24. An apparatus fabricated on a semiconductor substrate for determining a full match for a variable length search key, comprising:
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an embedded processor complex including a plurality of protocol processors and an internal control point processor that provide frame processing;
a plurality of hardware accelerator co-processors accessible to each protocol processor and providing high speed pattern searching, data manipulation, and frame parsing;
a plurality of programable memory devices that store a plurality of data structures that represent at least one search tree, wherein the data structures include a direct table, a pattern search control block and a leaf; and
an control memory arbiter that controls the access of each protocol processor to the plurality of memory devices. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33)
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34-45. -45. (canceled)
Specification